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SMP fence now ensure ordering for all kinds of memory transfers

This commit is contained in:
Dolu1990 2020-04-27 17:37:15 +02:00
parent 3fb123a64a
commit 0c59dd9ed3
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/vexriscv/ip/DataCache.scala
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@ -567,7 +567,7 @@ class DataCache(val p : DataCacheConfig) extends Component{
val consistancyCheck = (withInvalidate || withWriteResponse) generate new Area {
val fenceConsistent = (if(withInvalidate) sync.fenceConsistent else pending.done) && !io.cpu.writeBack.fenceValid && !io.cpu.memory.fenceValid //Pessimistic fence tracking
val totalyConsistent = (if(withInvalidate) sync.totalyConsistent else pending.done) && !(io.cpu.memory.isValid && io.cpu.memory.isWrite) && !(io.cpu.writeBack.isValid && io.cpu.memory.isWrite)
when(io.cpu.execute.isValid && (!io.cpu.execute.args.wr || isAmo)){
when(io.cpu.execute.isValid /*&& (!io.cpu.execute.args.wr || isAmo)*/){
when(!fenceConsistent || io.cpu.execute.totalyConsistent && !totalyConsistent){
io.cpu.execute.haltIt := True
}

2
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
View File

@ -236,7 +236,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
if(withLrSc) insert(MEMORY_FENCE_BACK) setWhen(input(MEMORY_LRSC))
if(withAmo) insert(MEMORY_FENCE_BACK) setWhen(input(MEMORY_AMO))
}
when(input(INSTRUCTION)(25)) { //RL but a bit pessimistic as it could be MEMORY_FENCE_BACK when the memory op isn't a read
when(input(INSTRUCTION)(25)) { //RL
if(withLrSc) insert(MEMORY_FENCE_FRONT) setWhen(input(MEMORY_LRSC))
if(withAmo) insert(MEMORY_FENCE_FRONT) setWhen(input(MEMORY_AMO))
}