Connect the UART interruption to the CPU
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568c7d1365
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@ -186,7 +186,8 @@ case class Murax(config : MuraxConfig) extends Component{
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)
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//Checkout plugins used to instanciate the CPU to connect them to the SoC
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val timerInterrupt = Bool
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val timerInterrupt = False
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val externalInterrupt = False
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var iBus : IBusSimpleBus = null
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var dBus : DBusSimpleBus = null
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var debugBus : DebugExtensionBus = null
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@ -202,7 +203,7 @@ case class Murax(config : MuraxConfig) extends Component{
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}
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}
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case plugin : CsrPlugin => {
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plugin.externalInterrupt := False
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plugin.externalInterrupt := externalInterrupt
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plugin.timerInterrupt := timerInterrupt
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}
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case plugin : DebugPlugin => plugin.debugClockDomain{
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@ -315,7 +316,7 @@ case class Murax(config : MuraxConfig) extends Component{
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}
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val specification = List[(SimpleBus,SizeMapping)](
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ram.bus -> (0x00000000l, onChipRamSize kB),
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ram.bus -> (0x00000000l, onChipRamSize kB),
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apbBridge.simpleBus -> (0xF0000000l, 1 MB)
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)
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@ -365,8 +366,10 @@ case class Murax(config : MuraxConfig) extends Component{
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txFifoDepth = 16,
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rxFifoDepth = 16
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)
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val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
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uartCtrl.io.uart <> io.uart
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externalInterrupt setWhen(uartCtrl.io.interrupt)
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val timer = new Area{
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val apb = Apb3(
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@ -394,7 +397,7 @@ case class Murax(config : MuraxConfig) extends Component{
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val interruptCtrlBridge = interruptCtrl.driveFrom(busCtrl,0x10)
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interruptCtrl.io.inputs(0) := timerA.io.full
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interruptCtrl.io.inputs(1) := timerB.io.full
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timerInterrupt := interruptCtrl.io.pendings.orR
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timerInterrupt setWhen(interruptCtrl.io.pendings.orR)
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}
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