Update murax readme
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README.md
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README.md
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@ -227,7 +227,6 @@ There is some measurements of Briey SoC timings and area :
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Cyclone V -> 126 Mhz 2,295 ALMs
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Cyclone IV -> 121 Mhz 4,781 LUT 3,713 FF
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Cyclone II -> 104 Mhz 4,902 LUT 3,718 FF
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```
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## Murax SoC
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@ -240,10 +239,11 @@ Murax is a very light SoC (fit in ICE40 FPGA) which could work without any exter
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- APB bus for peripherals
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- 32 GPIO pin
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- one 16 bits prescaler, two 16 bits timers
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- one UART with tx/rx fifo
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Depending the CPU configuration, on the ICE40-hx8k FPGA with icestorm for synthesis, the full SoC will get following area/performance :
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- RV32I interlocked stages => 53 Mhz, 2142 LC 0.37 DMIPS/Mhz
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- RV32I bypassed stages => 53 Mhz, 2463 LC 0.55 DMIPS/Mhz
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- RV32I interlocked stages => 51 Mhz, 2387 LC 0.37 DMIPS/Mhz
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- RV32I bypassed stages => 45 Mhz, 2718 LC 0.55 DMIPS/Mhz
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You can find its implementation there : src/main/scala/vexriscv/demo/Murax.scala
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@ -269,12 +269,19 @@ src/openocd -f tcl/interface/jtag_tcp.cfg -c "set MURAX_CPU0_YAML /home/spinalvm
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There is some measurements of Murax SoC timings and area for the 0.37 DMIPS/Mhz SoC version :
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```
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Murax ->
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Artix 7 -> 307 Mhz 884 LUT 1195 FF
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Cyclone V -> 149 Mhz 655 ALMs
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Cyclone IV -> 148 Mhz 1255 LUT 1171 FF
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Cyclone II -> 121 Mhz 1259 LUT 1170 FF
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ICE40-HX -> 53 Mhz 2142 LC (icestorm)
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Murax interlocked stages (0.37 DMIPS/Mhz) ->
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Artix 7 -> 306 Mhz 1021 LUT 1291 FF
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Cyclone V -> 173 Mhz 752 ALMs
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Cyclone IV -> 140 Mhz 1483 LUT 1,250 FF
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Cyclone II -> 127 Mhz 1484 LUT 1,249 FF
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ICE40-HX -> 51 Mhz 2387 LC (icestorm)
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MuraxFast bypassed stages (0.55 DMIPS/Mhz) ->
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Artix 7 -> 310 Mhz 1192 LUT 1388 FF
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Cyclone V -> 160 Mhz 893 ALMs
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Cyclone IV -> 142 Mhz 1726 LUT 1,284 FF
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Cyclone II -> 106 Mhz 1714 LUT 1,283 FF
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ICE40-HX -> 45 Mhz, 2718 LC (icestorm)
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```
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There is some scripts to generate the SoC and call the icestorm toolchain there : scripts/Murax/
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@ -21,3 +21,5 @@ time: bin/toplevel.bin
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prog : bin/toplevel.bin
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sudo iceprog -S bin/toplevel.bin
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clean :
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rm -rf bin
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