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VexRiscv
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Connect the UART interruption to the CPU

This commit is contained in:
Charles Papon 2017-07-31 17:20:47 +02:00
parent 568c7d1365
commit 0c9a39d3ce
1 changed files with 7 additions and 4 deletions
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9
src/main/scala/vexriscv/demo/Murax.scala
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@ -186,7 +186,8 @@ case class Murax(config : MuraxConfig) extends Component{
)
//Checkout plugins used to instanciate the CPU to connect them to the SoC
val timerInterrupt = Bool
val timerInterrupt = False
val externalInterrupt = False
var iBus : IBusSimpleBus = null
var dBus : DBusSimpleBus = null
var debugBus : DebugExtensionBus = null
@ -202,7 +203,7 @@ case class Murax(config : MuraxConfig) extends Component{
}
}
case plugin : CsrPlugin => {
plugin.externalInterrupt := False
plugin.externalInterrupt := externalInterrupt
plugin.timerInterrupt := timerInterrupt
}
case plugin : DebugPlugin => plugin.debugClockDomain{
@ -365,8 +366,10 @@ case class Murax(config : MuraxConfig) extends Component{
txFifoDepth = 16,
rxFifoDepth = 16
)
val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
uartCtrl.io.uart <> io.uart
externalInterrupt setWhen(uartCtrl.io.interrupt)
val timer = new Area{
val apb = Apb3(
@ -394,7 +397,7 @@ case class Murax(config : MuraxConfig) extends Component{
val interruptCtrlBridge = interruptCtrl.driveFrom(busCtrl,0x10)
interruptCtrl.io.inputs(0) := timerA.io.full
interruptCtrl.io.inputs(1) := timerB.io.full
timerInterrupt := interruptCtrl.io.pendings.orR
timerInterrupt setWhen(interruptCtrl.io.pendings.orR)
}