IBusDBusCachedTightlyCoupledRam add missing write mask

This commit is contained in:
Dolu1990 2023-11-02 11:59:33 +01:00
parent 281818af9c
commit 0f17b395bd
1 changed files with 2 additions and 1 deletions

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@ -680,7 +680,8 @@ class IBusDBusCachedTightlyCoupledRam(mapping : SizeMapping, withIBus : Boolean
address = (dbus.address >> 2).resized,
data = dbus.write_data,
enable = dbus.enable,
write = dbus.write_enable
write = dbus.write_enable,
mask = dbus.write_mask
)
}
val i = withIBus generate new Area {