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VexRiscv
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fix synthesis bench

This commit is contained in:
Dolu1990 2021-02-04 12:41:31 +01:00
parent 8eb8356dea
commit 0f1ca72171
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/vexriscv/demo/SynthesisBench.scala
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@ -217,7 +217,7 @@ object VexRiscvSynthesisBench {
frequencyTarget = 50 MHz,
vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
workspacePath=workspace + "_area",
toplevelPath=rtl.getRtlPath(),
rtl=rtl,
family=getFamilyName(),
device="xcku035-fbva900-3-e"
)
@ -230,7 +230,7 @@ object VexRiscvSynthesisBench {
frequencyTarget = 800 MHz,
vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
workspacePath=workspace + "_fmax",
toplevelPath=rtl.getRtlPath(),
rtl=rtl,
family=getFamilyName(),
device="xcku035-fbva900-3-e"
)
@ -243,7 +243,7 @@ object VexRiscvSynthesisBench {
frequencyTarget = 50 MHz,
vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
workspacePath=workspace + "_area",
toplevelPath=rtl.getRtlPath(),
rtl=rtl,
family=getFamilyName(),
device="xcku3p-ffvd900-3-e"
)
@ -256,7 +256,7 @@ object VexRiscvSynthesisBench {
frequencyTarget = 800 MHz,
vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
workspacePath=workspace + "_fmax",
toplevelPath=rtl.getRtlPath(),
rtl=rtl,
family=getFamilyName(),
device="xcku3p-ffvd900-3-e"
)