Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add DBusSimple early injection feature (better DMIPS)

This commit is contained in:
Charles Papon 2017-07-26 23:36:25 +02:00
parent 6d117f5c81
commit 10d282b2ef
2 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/vexriscv/TestsWorkspace.scala
View File

@ -58,7 +58,8 @@ object TestsWorkspace {
), ),
// new DBusSimplePlugin( // new DBusSimplePlugin(
// catchAddressMisaligned = true, // catchAddressMisaligned = true,
// catchAccessFault = true // catchAccessFault = true,
// earlyInjection = false
// ), // ),
new DBusCachedPlugin( new DBusCachedPlugin(
config = new DataCacheConfig( config = new DataCacheConfig(

12
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
View File

@ -133,7 +133,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
} }
class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Boolean) extends Plugin[VexRiscv]{ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Boolean, earlyInjection : Boolean = false) extends Plugin[VexRiscv]{
var dBus : DBusSimpleBus = null var dBus : DBusSimpleBus = null
@ -161,7 +161,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
SRC2_CTRL -> Src2CtrlEnum.IMI, SRC2_CTRL -> Src2CtrlEnum.IMI,
REGFILE_WRITE_VALID -> True, REGFILE_WRITE_VALID -> True,
BYPASSABLE_EXECUTE_STAGE -> False, BYPASSABLE_EXECUTE_STAGE -> False,
BYPASSABLE_MEMORY_STAGE -> False BYPASSABLE_MEMORY_STAGE -> Bool(earlyInjection)
) )
val storeActions = stdActions ++ List( val storeActions = stdActions ++ List(
@ -249,8 +249,9 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
} }
//Reformat read responses, REGFILE_WRITE_DATA overriding //Reformat read responses, REGFILE_WRITE_DATA overriding
writeBack plug new Area { val injectionStage = if(earlyInjection) memory else writeBack
import writeBack._ injectionStage plug new Area {
import injectionStage._
val rspShifted = MEMORY_READ_DATA() val rspShifted = MEMORY_READ_DATA()
@ -271,7 +272,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
input(REGFILE_WRITE_DATA) := rspFormated input(REGFILE_WRITE_DATA) := rspFormated
} }
assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(INSTRUCTION)(5) && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend") if(!earlyInjection)
assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(INSTRUCTION)(5) && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend")
} }
} }
} }