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Add DBusSimple early injection feature (better DMIPS)

This commit is contained in:
Charles Papon 2017-07-26 23:36:25 +02:00
parent 6d117f5c81
commit 10d282b2ef
2 changed files with 9 additions and 6 deletions
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3
src/main/scala/vexriscv/TestsWorkspace.scala
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@ -58,7 +58,8 @@ object TestsWorkspace {
),
// new DBusSimplePlugin(
// catchAddressMisaligned = true,
// catchAccessFault = true
// catchAccessFault = true,
// earlyInjection = false
// ),
new DBusCachedPlugin(
config = new DataCacheConfig(

10
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
View File

@ -133,7 +133,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
}
class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Boolean) extends Plugin[VexRiscv]{
class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Boolean, earlyInjection : Boolean = false) extends Plugin[VexRiscv]{
var dBus : DBusSimpleBus = null
@ -161,7 +161,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
SRC2_CTRL -> Src2CtrlEnum.IMI,
REGFILE_WRITE_VALID -> True,
BYPASSABLE_EXECUTE_STAGE -> False,
BYPASSABLE_MEMORY_STAGE -> False
BYPASSABLE_MEMORY_STAGE -> Bool(earlyInjection)
)
val storeActions = stdActions ++ List(
@ -249,8 +249,9 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
}
//Reformat read responses, REGFILE_WRITE_DATA overriding
writeBack plug new Area {
import writeBack._
val injectionStage = if(earlyInjection) memory else writeBack
injectionStage plug new Area {
import injectionStage._
val rspShifted = MEMORY_READ_DATA()
@ -271,6 +272,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
input(REGFILE_WRITE_DATA) := rspFormated
}
if(!earlyInjection)
assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(INSTRUCTION)(5) && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend")
}
}