Add DebugPlugin avalon
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@ -6,6 +6,7 @@ import VexRiscv.ip._
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba3.apb.{Apb3Config, Apb3}
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import spinal.lib.bus.avalon.{AvalonMMConfig, AvalonMM}
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case class DebugExtensionCmd() extends Bundle{
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@ -19,14 +20,14 @@ case class DebugExtensionRsp() extends Bundle{
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case class DebugExtensionBus() extends Bundle with IMasterSlave{
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val cmd = Stream(DebugExtensionCmd())
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val rsp = DebugExtensionRsp() //One cycle latency
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val rsp = DebugExtensionRsp() //zero cycle latency
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override def asMaster(): Unit = {
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master(cmd)
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in(rsp)
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}
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def toApb3(): Apb3 ={
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def fromApb3(): Apb3 ={
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val apb = Apb3(Apb3Config(
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addressWidth = 8,
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dataWidth = 32,
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@ -43,6 +44,20 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
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apb
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}
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def fromAvalon(): AvalonMM ={
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val bus = AvalonMM(AvalonMMConfig.fixed(addressWidth = 8,dataWidth = 32, readLatency = 0))
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cmd.valid := bus.read || bus.write
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cmd.wr := bus.write
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cmd.address := bus.address
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cmd.data := bus.writeData
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bus.waitRequestn := cmd.ready
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bus.readData := rsp.data
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bus
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}
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}
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case class DebugExtensionIo() extends Bundle with IMasterSlave{
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@ -304,7 +304,7 @@ class Briey(config: BrieyConfig) extends Component{
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}
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case plugin : DebugPlugin => {
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resetCtrl.coreResetUnbuffered setWhen(plugin.io.resetOut)
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debugBus = plugin.io.bus.toApb3()
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debugBus = plugin.io.bus.fromApb3()
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}
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case _ =>
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}
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@ -132,6 +132,10 @@ object VexRiscvAvalon{
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plugin.dBus.asDirectionLess()
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master(plugin.dBus.toAvalon()).setName("dBusAvalon")
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}
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case plugin: DebugPlugin => {
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plugin.io.bus.asDirectionLess()
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slave(plugin.io.bus.fromAvalon()).setName("debugBusAvalon")
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}
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case _ =>
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}
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}
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