Merge remote-tracking branch 'upstream/master' into pmp

README.md

@@ -296,7 +296,7 @@ sbt "runMain vexriscv.demo.Briey"
 To run the verilator simulation of the Briey SoC, which can then be connected to OpenOCD/GDB, first get these dependencies:
 
 ```sh
-sudo apt-get install build-essential xorg-dev libudev-dev libts-dev libgl1-mesa-dev libglu1-mesa-dev libasound2-dev libpulse-dev libopenal-dev libogg-dev libvorbis-dev libaudiofile-dev libpng12-dev libfreetype6-dev libusb-dev libdbus-1-dev zlib1g-dev libdirectfb-dev libsdl2-dev
+sudo apt-get install build-essential xorg-dev libudev-dev libgl1-mesa-dev libglu1-mesa-dev libasound2-dev libpulse-dev libopenal-dev libogg-dev libvorbis-dev libaudiofile-dev libpng12-dev libfreetype6-dev libusb-dev libdbus-1-dev zlib1g-dev libdirectfb-dev libsdl2-dev
 ```
 
 Then go in `src/test/cpp/briey` and run the simulation with (UART TX is printed in the terminal, VGA is displayed in a GUI):
@@ -412,7 +412,7 @@ Note that VexRiscv can run Linux on both cache full and cache less design.
 
 A prebuild GCC toolsuite can be found here:
 
-- https://www.sifive.com/products/tools/  => SiFive GNU Embedded Toolchain
+- https://www.sifive.com/software/  => Prebuilt RISC‑V GCC Toolchain and Emulator
 
 The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/riscv/__contentOfThisPreBuild__
 

src/main/scala/vexriscv/plugin/CsrPlugin.scala

@@ -1035,18 +1035,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
         val readData = Bits(32 bits)
         val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE)
         val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE)
-        val writeEnable = writeInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// &&  readDataRegValid
+        val writeEnable = writeInstruction && !arbitration.isStuck
-        val readEnable  = readInstruction  && ! blockedBySideEffects && !arbitration.isStuckByOthers// && !readDataRegValid
+        val readEnable  = readInstruction  && !arbitration.isStuck
-        //arbitration.isStuckByOthers, in case of the hazardPlugin is in the executeStage
-
-
-//        def readDataReg = memory.input(REGFILE_WRITE_DATA)  //PIPE OPT
-//        val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck)
-//        val writeDataEnable = input(INSTRUCTION)(13) ? writeSrc | B"xFFFFFFFF"
-//        val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux(
-//          False -> writeSrc,
-//          True -> Mux(input(INSTRUCTION)(12), ~writeSrc,  writeSrc)
-//        )
 
         val readToWriteData = CombInit(readData)
         val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux(
@@ -1161,7 +1151,11 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
             }
           }
 
-          illegalAccess setWhen(privilege < csrAddress(9 downto 8).asUInt)
+          when(privilege < csrAddress(9 downto 8).asUInt){
+            illegalAccess := True
+            readInstruction := False
+            writeInstruction := False
+          }
           illegalAccess clearWhen(!arbitration.isValid || !input(IS_CSR))
         }
       }

src/main/scala/vexriscv/plugin/DebugPlugin.scala

@@ -195,8 +195,9 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount :
         }
       }
 
+      val allowEBreak = if(!pipeline.serviceExist(classOf[PrivilegeService])) True else pipeline.service(classOf[PrivilegeService]).isMachine()
 
-      decode.insert(DO_EBREAK) := !haltIt && (decode.input(IS_EBREAK) || hardwareBreakpoints.map(hb => hb.valid && hb.pc === (decode.input(PC) >> 1)).foldLeft(False)(_ || _))
+      decode.insert(DO_EBREAK) := !haltIt && (decode.input(IS_EBREAK) || hardwareBreakpoints.map(hb => hb.valid && hb.pc === (decode.input(PC) >> 1)).foldLeft(False)(_ || _)) && allowEBreak
       when(execute.arbitration.isValid && execute.input(DO_EBREAK)){
         execute.arbitration.haltByOther := True
         busReadDataReg := execute.input(PC).asBits