Fix CFU / FPU decoder stage fork on illegal instruction
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@ -182,12 +182,13 @@ class CfuPlugin(val stageCount : Int,
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}
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}
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}
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}
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if(withEnable) when(decode.input(CFU_ENABLE) && !csr.en){
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if(withEnable) when(decode.insert(CFU_ENABLE) && !csr.en){
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pipeline.service(classOf[DecoderService]).forceIllegal()
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pipeline.service(classOf[DecoderService]).forceIllegal()
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}
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}
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forkStage plug new Area{
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forkStage plug new Area{
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import forkStage._
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import forkStage._
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input(CFU_ENABLE).clearWhen(!input(LEGAL_INSTRUCTION))
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val hazard = stages.dropWhile(_ != forkStage).tail.map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR
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val hazard = stages.dropWhile(_ != forkStage).tail.map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR
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val scheduleWish = arbitration.isValid && input(CFU_ENABLE)
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val scheduleWish = arbitration.isValid && input(CFU_ENABLE)
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val schedule = scheduleWish && !hazard
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val schedule = scheduleWish && !hazard
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@ -243,7 +243,7 @@ class FpuPlugin(externalFpu : Boolean = false,
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decode plug new Area{
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decode plug new Area{
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import decode._
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import decode._
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val trap = decode.input(FPU_ENABLE) && csr.fs === 0 && !stagesFromExecute.map(_.arbitration.isValid).orR
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val trap = insert(FPU_ENABLE) && csr.fs === 0 && !stagesFromExecute.map(_.arbitration.isValid).orR
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when(trap){
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when(trap){
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pipeline.service(classOf[DecoderService]).forceIllegal()
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pipeline.service(classOf[DecoderService]).forceIllegal()
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}
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}
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@ -253,6 +253,7 @@ class FpuPlugin(externalFpu : Boolean = false,
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val hazard = csr.pendings.msb || csr.csrActive || csr.fs === 0
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val hazard = csr.pendings.msb || csr.csrActive || csr.fs === 0
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input(FPU_ENABLE).clearWhen(!input(LEGAL_INSTRUCTION))
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arbitration.haltItself setWhen(arbitration.isValid && input(FPU_ENABLE) && hazard)
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arbitration.haltItself setWhen(arbitration.isValid && input(FPU_ENABLE) && hazard)
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arbitration.haltItself setWhen(port.cmd.isStall)
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arbitration.haltItself setWhen(port.cmd.isStall)
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