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VexRiscv
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Fix CFU / FPU decoder stage fork on illegal instruction

This commit is contained in:
Charles Papon 2023-03-04 12:20:53 +01:00
parent cf70bc6b1f
commit 153445ff21
2 changed files with 4 additions and 2 deletions
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3
src/main/scala/vexriscv/plugin/CfuPlugin.scala
View File

@ -182,12 +182,13 @@ class CfuPlugin(val stageCount : Int,
}
}
if(withEnable) when(decode.input(CFU_ENABLE) && !csr.en){
if(withEnable) when(decode.insert(CFU_ENABLE) && !csr.en){
pipeline.service(classOf[DecoderService]).forceIllegal()
}
forkStage plug new Area{
import forkStage._
input(CFU_ENABLE).clearWhen(!input(LEGAL_INSTRUCTION))
val hazard = stages.dropWhile(_ != forkStage).tail.map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR
val scheduleWish = arbitration.isValid && input(CFU_ENABLE)
val schedule = scheduleWish && !hazard

3
src/main/scala/vexriscv/plugin/FpuPlugin.scala
View File

@ -243,7 +243,7 @@ class FpuPlugin(externalFpu : Boolean = false,
decode plug new Area{
import decode._
val trap = decode.input(FPU_ENABLE) && csr.fs === 0 && !stagesFromExecute.map(_.arbitration.isValid).orR
val trap = insert(FPU_ENABLE) && csr.fs === 0 && !stagesFromExecute.map(_.arbitration.isValid).orR
when(trap){
pipeline.service(classOf[DecoderService]).forceIllegal()
}
@ -253,6 +253,7 @@ class FpuPlugin(externalFpu : Boolean = false,
val hazard = csr.pendings.msb || csr.csrActive || csr.fs === 0
input(FPU_ENABLE).clearWhen(!input(LEGAL_INSTRUCTION))
arbitration.haltItself setWhen(arbitration.isValid && input(FPU_ENABLE) && hazard)
arbitration.haltItself setWhen(port.cmd.isStall)