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VexRiscv
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Give name to inter stages registers

This commit is contained in:
Dolu1990 2018-05-27 23:39:49 +02:00
parent c4f33b30e2
commit 1752b5f184
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/vexriscv/Pipeline.scala
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@ -100,7 +100,7 @@ trait Pipeline {
inputDefault := stage.inserts(key) inputDefault := stage.inserts(key)
} else { } else {
val stageBefore = stages(stageIndex - 1) val stageBefore = stages(stageIndex - 1)
inputDefault := RegNextWhen(stageBefore.output(key), !stage.arbitration.isStuck) inputDefault := RegNextWhen(stageBefore.output(key), !stage.arbitration.isStuck).setName(s"${stageBefore.getName()}_to_${stage.getName()}_${key.getName()}")
} }
} }
} }