Give name to inter stages registers

2018-05-27 23:39:49 +02:00 · 2018-05-27 23:39:49 +02:00 · 1752b5f184
parent c4f33b30e2
commit 1752b5f184
1 changed files with 1 additions and 1 deletions
--- a/src/main/scala/vexriscv/Pipeline.scala
+++ b/src/main/scala/vexriscv/Pipeline.scala
@ -100,7 +100,7 @@ trait Pipeline {
            inputDefault := stage.inserts(key)
          } else {
            val stageBefore = stages(stageIndex - 1)
-            inputDefault := RegNextWhen(stageBefore.output(key), !stage.arbitration.isStuck)
+            inputDefault := RegNextWhen(stageBefore.output(key), !stage.arbitration.isStuck).setName(s"${stageBefore.getName()}_to_${stage.getName()}_${key.getName()}")
          }
        }
      }