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IBusCachedPlugin add asyncTagMemory option

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This commit is contained in:
Charles Papon 2017-04-05 14:25:11 +02:00
parent 2b24cbc8e1
commit 179e7f7b4c
2 changed files with 32 additions and 24 deletions
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54
src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala
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@ -12,7 +12,8 @@ case class InstructionCacheConfig( cacheSize : Int,
addressWidth : Int,
cpuDataWidth : Int,
memDataWidth : Int,
catchAccessFault : Boolean){
catchAccessFault : Boolean,
asyncTagMemory : Boolean){
def burstSize = bytePerLine*8/memDataWidth
}
@ -282,7 +283,12 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
val waysRead = for(way <- ways) yield new Area{
val readAddress = Mux(io.cpu.fetch.isStuck,io.cpu.fetch.address,io.cpu.prefetch.address)
val tag = way.tags.readSync(readAddress(lineRange))
// val readAddress = io.cpu.prefetch.address
val tag = if(asyncTagMemory)
way.tags.readAsync(io.cpu.fetch.address(lineRange))
else
way.tags.readSync(readAddress(lineRange))
val data = way.datas.readSync(readAddress(lineRange.high downto wordRange.low))
// val readAddress = request.address
// val tag = way.tags.readAsync(readAddress(lineRange))
@ -314,25 +320,25 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
io.flush.cmd.ready := !(lineLoader.request.valid || io.cpu.fetch.isValid)
}
object InstructionCacheMain{
def main(args: Array[String]) {
implicit val p = InstructionCacheConfig(
cacheSize =4096,
bytePerLine =32,
wayCount = 1,
wrappedMemAccess = true,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchAccessFault = true)
// val io = new Bundle{
// val cpu = slave(InstructionCacheCpuBus())
// val mem = master(InstructionCacheMemBus())
// }
SpinalVhdl(new InstructionCache(p))
}
}
//
//object InstructionCacheMain{
//
// def main(args: Array[String]) {
// implicit val p = InstructionCacheConfig(
// cacheSize =4096,
// bytePerLine =32,
// wayCount = 1,
// wrappedMemAccess = true,
// addressWidth = 32,
// cpuDataWidth = 32,
// memDataWidth = 32,
// catchAccessFault = true)
// // val io = new Bundle{
// // val cpu = slave(InstructionCacheCpuBus())
// // val mem = master(InstructionCacheMemBus())
// // }
//
// SpinalVhdl(new InstructionCache(p))
// }
//}
//

2
src/test/cpp/testA/main.cpp
View file

@ -457,7 +457,9 @@ public:
top->iBus_rsp_valid = 0;
if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I(7) < 100)){
ws->iBusAccess(address,&top->iBus_rsp_payload_data,&error);
#ifdef CSR
top->iBus_rsp_payload_error = error;
#endif
pendingCount--;
address = (address & ~0x1F) + ((address + 4) & 0x1F);
top->iBus_rsp_valid = 1;