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VexRiscv
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This commit is contained in:
Dolu1990 2018-04-09 09:18:08 +02:00
parent 4dd2997ad5
commit 19d5d1ecf1
2 changed files with 21 additions and 20 deletions
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33
src/main/scala/vexriscv/plugin/Fetcher.scala
View File

@ -172,13 +172,13 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
}) })
val iBusCmd = new Area { // val iBusCmd = new Area {
def input = fetchPc.output // def input = fetchPc.output
//
// ... // // ...
//
val output = Stream(UInt(32 bits)) // val output = Stream(UInt(32 bits))
} // }
case class FetchRsp() extends Bundle { case class FetchRsp() extends Bundle {
val pc = UInt(32 bits) val pc = UInt(32 bits)
@ -188,21 +188,20 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
val iBusRsp = new Area { val iBusRsp = new Area {
val inputStages = Vec(Stream(UInt(32 bits)), cmdToRspStageCount) val input = Stream(UInt(32 bits))
val pipeline = Vec(Stream(UInt(32 bits)), cmdToRspStageCount)
for(i <- 0 until cmdToRspStageCount) { for(i <- 0 until cmdToRspStageCount) {
// val doFlush = if(i == cmdToRspStageCount- 1 && ???) killLastStage else flush // val doFlush = if(i == cmdToRspStageCount- 1 && ???) killLastStage else flush
inputStages(i) << {i match { pipeline(i) << {i match {
case 0 => iBusCmd.output.m2sPipeWithFlush(flush, relaxedPcCalculation) case 0 => input.m2sPipeWithFlush(flush, relaxedPcCalculation)
case _ => inputStages(i-1)/*.haltWhen(fetcherHalt)*/.m2sPipeWithFlush(flush) case _ => pipeline(i-1)/*.haltWhen(fetcherHalt)*/.m2sPipeWithFlush(flush)
}} }}
} }
def input = inputStages.last
// ... // ...
val join = Stream(FetchRsp()) val outputBeforeStage = Stream(FetchRsp())
val output = if(rspStageGen) join.m2sPipeWithFlush(flush) else join val output = if(rspStageGen) outputBeforeStage.m2sPipeWithFlush(flush) else outputBeforeStage
} }
val decompressor = ifGen(decodePcGen)(new Area{ val decompressor = ifGen(decodePcGen)(new Area{
@ -255,8 +254,8 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
decodeNextPc := decodePc.pcReg decodeNextPc := decodePc.pcReg
}else { }else {
val lastStageStream = if(injectorStage) inputBeforeHalt val lastStageStream = if(injectorStage) inputBeforeHalt
else if(rspStageGen) iBusRsp.join else if(rspStageGen) iBusRsp.outputBeforeStage
else if(cmdToRspStageCount > 1)iBusRsp.inputStages(cmdToRspStageCount-2) else if(cmdToRspStageCount > 1)iBusRsp.pipeline(cmdToRspStageCount-2)
else throw new Exception("Fetch should at least have two stages") else throw new Exception("Fetch should at least have two stages")
// when(fetcherHalt){ // when(fetcherHalt){

8
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View File

@ -132,7 +132,9 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
pipeline plug new FetchArea(pipeline) { pipeline plug new FetchArea(pipeline) {
val cmd = new Area { val cmd = new Area {
import iBusCmd._ def input = fetchPc.output
def output = iBusRsp.input
output << input.continueWhen(iBus.cmd.fire) output << input.continueWhen(iBus.cmd.fire)
//Avoid sending to many iBus cmd //Avoid sending to many iBus cmd
@ -161,12 +163,12 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
rspBuffer.io.flush := flush rspBuffer.io.flush := flush
val fetchRsp = FetchRsp() val fetchRsp = FetchRsp()
fetchRsp.pc := input.payload fetchRsp.pc := pipeline.last.payload
fetchRsp.rsp := rspBuffer.io.pop.payload fetchRsp.rsp := rspBuffer.io.pop.payload
fetchRsp.rsp.error.clearWhen(!rspBuffer.io.pop.valid) //Avoid interference with instruction injection from the debug plugin fetchRsp.rsp.error.clearWhen(!rspBuffer.io.pop.valid) //Avoid interference with instruction injection from the debug plugin
val join = StreamJoin(Seq(input, rspBuffer.io.pop), fetchRsp) val join = StreamJoin(Seq(pipeline.last, rspBuffer.io.pop), fetchRsp)
output << (if(rspStageGen) join.m2sPipeWithFlush(flush) else join) output << (if(rspStageGen) join.m2sPipeWithFlush(flush) else join)
} }
} }