wip
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4dd2997ad5
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@ -172,13 +172,13 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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})
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val iBusCmd = new Area {
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def input = fetchPc.output
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// ...
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val output = Stream(UInt(32 bits))
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}
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// val iBusCmd = new Area {
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// def input = fetchPc.output
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//
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// // ...
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//
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// val output = Stream(UInt(32 bits))
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// }
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case class FetchRsp() extends Bundle {
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val pc = UInt(32 bits)
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@ -188,21 +188,20 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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val iBusRsp = new Area {
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val inputStages = Vec(Stream(UInt(32 bits)), cmdToRspStageCount)
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val input = Stream(UInt(32 bits))
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val pipeline = Vec(Stream(UInt(32 bits)), cmdToRspStageCount)
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for(i <- 0 until cmdToRspStageCount) {
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// val doFlush = if(i == cmdToRspStageCount- 1 && ???) killLastStage else flush
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inputStages(i) << {i match {
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case 0 => iBusCmd.output.m2sPipeWithFlush(flush, relaxedPcCalculation)
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case _ => inputStages(i-1)/*.haltWhen(fetcherHalt)*/.m2sPipeWithFlush(flush)
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pipeline(i) << {i match {
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case 0 => input.m2sPipeWithFlush(flush, relaxedPcCalculation)
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case _ => pipeline(i-1)/*.haltWhen(fetcherHalt)*/.m2sPipeWithFlush(flush)
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}}
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}
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def input = inputStages.last
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// ...
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val join = Stream(FetchRsp())
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val output = if(rspStageGen) join.m2sPipeWithFlush(flush) else join
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val outputBeforeStage = Stream(FetchRsp())
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val output = if(rspStageGen) outputBeforeStage.m2sPipeWithFlush(flush) else outputBeforeStage
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}
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val decompressor = ifGen(decodePcGen)(new Area{
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@ -255,8 +254,8 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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decodeNextPc := decodePc.pcReg
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}else {
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val lastStageStream = if(injectorStage) inputBeforeHalt
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else if(rspStageGen) iBusRsp.join
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else if(cmdToRspStageCount > 1)iBusRsp.inputStages(cmdToRspStageCount-2)
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else if(rspStageGen) iBusRsp.outputBeforeStage
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else if(cmdToRspStageCount > 1)iBusRsp.pipeline(cmdToRspStageCount-2)
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else throw new Exception("Fetch should at least have two stages")
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// when(fetcherHalt){
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@ -132,7 +132,9 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
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pipeline plug new FetchArea(pipeline) {
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val cmd = new Area {
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import iBusCmd._
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def input = fetchPc.output
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def output = iBusRsp.input
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output << input.continueWhen(iBus.cmd.fire)
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//Avoid sending to many iBus cmd
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@ -161,12 +163,12 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
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rspBuffer.io.flush := flush
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val fetchRsp = FetchRsp()
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fetchRsp.pc := input.payload
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fetchRsp.pc := pipeline.last.payload
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fetchRsp.rsp := rspBuffer.io.pop.payload
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fetchRsp.rsp.error.clearWhen(!rspBuffer.io.pop.valid) //Avoid interference with instruction injection from the debug plugin
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val join = StreamJoin(Seq(input, rspBuffer.io.pop), fetchRsp)
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val join = StreamJoin(Seq(pipeline.last, rspBuffer.io.pop), fetchRsp)
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output << (if(rspStageGen) join.m2sPipeWithFlush(flush) else join)
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}
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}
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