Make the [ID]TLB size configurable from Litex

src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala

@@ -182,7 +182,9 @@ object VexRiscvSmpClusterGen {
                      externalFpu : Boolean = true,
                      simHalt : Boolean = false,
                      regfileRead : RegFileReadKind = plugin.ASYNC,
-                     rvc : Boolean = false
+                     rvc : Boolean = false,
+                     iTlbSize : Int = 4,
+                     dTlbSize : Int = 4
                     ) = {
     assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
     assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
@@ -219,7 +221,7 @@ object VexRiscvSmpClusterGen {
             reducedBankWidth = true
           ),
           memoryTranslatorPortConfig = MmuPortConfig(
-            portTlbSize = 4,
+            portTlbSize = iTlbSize,
             latency = 1,
             earlyRequireMmuLockup = true,
             earlyCacheHits = true
@@ -247,7 +249,7 @@ object VexRiscvSmpClusterGen {
             withWriteAggregation = dBusWidth > 32
           ),
           memoryTranslatorPortConfig = MmuPortConfig(
-            portTlbSize = 4,
+            portTlbSize = dTlbSize,
             latency = 1,
             earlyRequireMmuLockup = true,
             earlyCacheHits = true

src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala

@@ -118,6 +118,8 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
   var rvc = false
   var netlistDirectory = "."
   var netlistName = "VexRiscvLitexSmpCluster"
+  var iTlbSize = 4
+  var dTlbSize = 4
   assert(new scopt.OptionParser[Unit]("VexRiscvLitexSmpClusterCmdGen") {
     help("help").text("prints this usage text")
     opt[Unit]("coherent-dma") action { (v, c) => coherentDma = true }
@@ -137,6 +139,8 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
     opt[String]("fpu" ) action { (v, c) => fpu = v.toBoolean  }
     opt[String]("cpu-per-fpu") action { (v, c) => cpuPerFpu = v.toInt }
     opt[String]("rvc") action { (v, c) => rvc = v.toBoolean }
+    opt[String]("itlb-size") action { (v, c) => iTlbSize = v.toInt }
+    opt[String]("dtlb-size") action { (v, c) => dTlbSize = v.toInt }
   }.parse(args))
 
   val coherency = coherentDma || cpuCount > 1
@@ -161,7 +165,9 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
           externalFpu = fpu,
           loadStoreWidth = if(fpu) 64 else 32,
           rvc = rvc,
-          injectorStage = rvc
+          injectorStage = rvc,
+	  iTlbSize = iTlbSize,
+	  dTlbSize = dTlbSize
         )
         if(aesInstruction) c.add(new AesPlugin)
         c