Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fix #178

This commit is contained in:
Dolu1990 2021-05-04 21:09:42 +02:00
parent fa2899a1a2
commit e78c0546a0
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -956,9 +956,9 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
targetPrivilege := exceptionPortCtrl.exceptionTargetPrivilege
}
val trapCause = CombInit(interrupt.code)
val trapCause = CombInit(interrupt.code.resize(trapCodeWidth))
if(exceptionPortCtrl != null) when( hadException){
trapCause := exceptionPortCtrl.exceptionContext.code
trapCause := exceptionPortCtrl.exceptionContext.code.resized
}
val xtvec = Xtvec().assignDontCare()