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xip typo

This commit is contained in:
Dolu1990 2018-09-23 22:06:21 +02:00
parent 86efb75f6a
commit 1e3b75ef1d
3 changed files with 25 additions and 25 deletions
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42
scripts/Murax/iCE40-hx8k_breakout_board_xip/toplevel.v
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@ -37,20 +37,20 @@ module toplevel(
assign io_led = io_gpioA_write[7 : 0];
wire [1:0] io_xpi_sclk_write;
wire io_xpi_data_0_writeEnable;
wire [1:0] io_xpi_data_0_read;
wire [1:0] io_xpi_data_0_write;
wire io_xpi_data_1_writeEnable;
wire [1:0] io_xpi_data_1_read;
wire [1:0] io_xpi_data_1_write;
wire [0:0] io_xpi_ss;
wire [1:0] io_xip_sclk_write;
wire io_xip_data_0_writeEnable;
wire [1:0] io_xip_data_0_read;
wire [1:0] io_xip_data_0_write;
wire io_xip_data_1_writeEnable;
wire [1:0] io_xip_data_1_read;
wire [1:0] io_xip_data_1_write;
wire [0:0] io_xip_ss;
assign io_P12 = io_xpi_data_0_write[0];
assign io_xpi_data_1_read[0] = io_P11;
assign io_xpi_data_1_read[1] = io_P11;
assign io_R11 = io_xpi_sclk_write[0];
assign io_R12 = io_xpi_ss[0];
assign io_P12 = io_xip_data_0_write[0];
assign io_xip_data_1_read[0] = io_P11;
assign io_xip_data_1_read[1] = io_P11;
assign io_R11 = io_xip_sclk_write[0];
assign io_R12 = io_xip_ss[0];
Murax murax (
.io_asyncReset(0),
@ -64,13 +64,13 @@ module toplevel(
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd(io_B12),
.io_uart_rxd(io_B10),
.io_xpi_sclk_write(io_xpi_sclk_write),
.io_xpi_data_0_writeEnable(io_xpi_data_0_writeEnable),
.io_xpi_data_0_read(io_xpi_data_0_read),
.io_xpi_data_0_write(io_xpi_data_0_write),
.io_xpi_data_1_writeEnable(io_xpi_data_1_writeEnable),
.io_xpi_data_1_read(io_xpi_data_1_read),
.io_xpi_data_1_write(io_xpi_data_1_write),
.io_xpi_ss(io_xpi_ss)
.io_xip_sclk_write(io_xip_sclk_write),
.io_xip_data_0_writeEnable(io_xip_data_0_writeEnable),
.io_xip_data_0_read(io_xip_data_0_read),
.io_xip_data_0_write(io_xip_data_0_write),
.io_xip_data_1_writeEnable(io_xip_data_1_writeEnable),
.io_xip_data_1_read(io_xip_data_1_read),
.io_xip_data_1_write(io_xip_data_1_write),
.io_xip_ss(io_xip_ss)
);
endmodule

6
src/main/scala/vexriscv/demo/Murax.scala
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@ -162,7 +162,7 @@ case class Murax(config : MuraxConfig) extends Component{
val gpioA = master(TriStateArray(gpioWidth bits))
val uart = master(Uart())
val xpi = ifGen(genXpi)(master(SpiDdrMaster(xipConfig.ctrl.spi)))
val xip = ifGen(genXpi)(master(SpiDdrMaster(xipConfig.ctrl.spi)))
}
@ -286,9 +286,9 @@ case class Murax(config : MuraxConfig) extends Component{
timerInterrupt setWhen(timer.io.interrupt)
apbMapping += timer.io.apb -> (0x20000, 4 kB)
val xpi = ifGen(genXpi)(new Area{
val xip = ifGen(genXpi)(new Area{
val ctrl = Apb3SpiDdrMasterCtrl(xipConfig)
ctrl.io.spi <> io.xpi
ctrl.io.spi <> io.xip
externalInterrupt setWhen(ctrl.io.interrupt)
apbMapping += ctrl.io.apb -> (0x1F000, 4 kB)

2
src/test/scala/vexriscv/MuraxSim.scala
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@ -47,7 +47,7 @@ object MuraxSim {
baudPeriod = uartBaudPeriod
)
if(config.xipConfig != null)dut.io.xpi.data(1).read #= 0
if(config.xipConfig != null)dut.io.xip.data(1).read #= 0
val guiThread = fork{
val guiToSim = mutable.Queue[Any]()