Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity

Fix d$ uncached writes exception handeling

Browse source
This commit is contained in:
Dolu1990 2020-06-06 22:12:32 +02:00
parent 760d2f74d0
commit 1f9fce6388
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/main/scala/vexriscv/ip/DataCache.scala
View file

@ -983,7 +983,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
when(bypassCache){
io.cpu.writeBack.data := ioMemRspMuxed
if(catchAccessError) io.cpu.writeBack.accessError := io.mem.rsp.valid && io.mem.rsp.error
if(catchAccessError) io.cpu.writeBack.accessError := !request.wr && pending.last && io.mem.rsp.valid && io.mem.rsp.error
} otherwise {
io.cpu.writeBack.data := dataMux
if(catchAccessError) io.cpu.writeBack.accessError := (waysHits & B(tagsReadRsp.map(_.error))) =/= 0