Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Update litex cluster to implement utime

This commit is contained in:
Dolu1990 2020-06-05 13:31:24 +02:00
parent d6455817e7
commit 760d2f74d0
3 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
View File

@ -40,6 +40,7 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
val externalSupervisorInterrupts = in Bits(p.cpuConfigs.size bits)
val jtag = slave(Jtag())
val debugReset = out Bool()
val time = in UInt(64 bits)
}
val cpus = for((cpuConfig, cpuId) <- p.cpuConfigs.zipWithIndex) yield new Area{
@ -61,6 +62,7 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
plugin.externalInterrupt := io.externalInterrupts(cpuId)
plugin.timerInterrupt := io.timerInterrupts(cpuId)
if (plugin.config.supervisorGen) plugin.externalInterruptS := io.externalSupervisorInterrupts(cpuId)
if (plugin.utime != null) plugin.utime := io.time
}
case plugin: DebugPlugin => debugClockDomain{
io.debugReset := RegNext(plugin.io.resetOut)
@ -517,6 +519,9 @@ object VexRiscvSmpClusterOpenSbi extends App{
var lastAddress = 0l
})
dut.clockDomain.onSamplings{
dut.io.time #= simTime()/10
for(i <- 0 until cpuCount; iMem = dut.io.iMems(i); ctx = iMemCtx(i)){
// if(iMem.cmd.valid.toBoolean && iMem.cmd.ready.toBoolean){
// val length = iMem.cmd.length.toInt + 1

1
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
View File

@ -57,6 +57,7 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
cluster.io.debugReset <> io.debugReset
cluster.io.timerInterrupts <> B(clint.harts.map(_.timerInterrupt))
cluster.io.softwareInterrupts <> B(clint.harts.map(_.softwareInterrupt))
cluster.io.time := clint.time
val dBusDecoder = BmbDecoderOutOfOrder(
p = cluster.io.dMem.p,

2
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexMpCluster.scala
View File

@ -58,6 +58,7 @@ case class VexRiscvLitexSmpMpCluster(p : VexRiscvLitexSmpMpClusterParameter,
cluster.io.debugReset <> io.debugReset
cluster.io.timerInterrupts <> B(clint.harts.map(_.timerInterrupt))
cluster.io.softwareInterrupts <> B(clint.harts.map(_.softwareInterrupt))
cluster.io.time := clint.time
val dBusDecoder = BmbDecoderOutOfOrder(
p = cluster.io.dMem.p,
@ -253,6 +254,7 @@ object VexRiscvLitexSmpMpClusterOpenSbi extends App{
(dut.io.peripheral.ADR.toLong << 2) match {
case 0xF0000000l => print(dut.io.peripheral.DAT_MOSI.toLong.toChar)
case 0xF0000004l => dut.io.peripheral.DAT_MISO #= (if (System.in.available() != 0) System.in.read() else 0xFFFFFFFFl)
case _ =>
// case 0xF0000004l => {
// val c = if(stdin.nonEmpty) {
// stdin.dequeue().toInt & 0xFF