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VexRiscv
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Fix FormalPlugin to pass liveness again.

This commit is contained in:
Dolu1990 2017-11-06 23:04:33 +01:00
parent 8098a03a9b
commit 200a73bea0
1 changed files with 9 additions and 3 deletions
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12
src/main/scala/vexriscv/plugin/FomalPlugin.scala
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@ -53,11 +53,14 @@ case class RvfiPort() extends Bundle with IMasterSlave {
//feature added //feature added
//Halt CPU on decoding exception //Halt CPU on decoding exception
//VexRiscv changes
//input(INSTRUCTION)(5) REGFILE_WRITE_VALID
//VexRiscv bug //VexRiscv bug
//1) pcManagerService.createJumpInterface(pipeline.execute) //1) pcManagerService.createJumpInterface(pipeline.execute)
// pcManagerService.createJumpInterface(if(earlyBranch) pipeline.execute else pipeline.memory) // pcManagerService.createJumpInterface(if(earlyBranch) pipeline.execute else pipeline.memory)
//2) input(INSTRUCTION)(5) REGFILE_WRITE_VALID //2) JALR => clear PC(0)
//3) JALR => clear PC(0)
class FomalPlugin extends Plugin[VexRiscv]{ class FomalPlugin extends Plugin[VexRiscv]{
var rvfi : RvfiPort = null var rvfi : RvfiPort = null
@ -114,11 +117,14 @@ class FomalPlugin extends Plugin[VexRiscv]{
} }
}) })
when(Delay(haltRequest, 5)){ //Give time for value propagation from decode stage to writeback stage when(Delay(haltRequest, 5, init=False)){ //Give time for value propagation from decode stage to writeback stage
rvfi.valid := True rvfi.valid := True
rvfi.trap := True rvfi.trap := True
rvfi.halt := True rvfi.halt := True
} }
val haltFired = RegInit(False) setWhen(rvfi.valid && rvfi.halt)
rvfi.valid clearWhen(haltFired)
} }
} }
} }