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Fix regression test debugPlugin bus

This commit is contained in:
Charles Papon 2017-05-28 17:41:09 +02:00
parent 8dddc7e334
commit 213e154b40
4 changed files with 83 additions and 123 deletions
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2
src/main/scala/SpinalRiscv/Plugin/CsrPlugin.scala
View File

@ -273,7 +273,7 @@ class CsrPlugin(config : MachineCsrConfig) extends Plugin[VexRiscv] with Excepti
val exceptionValids = Vec(Bool,stages.length)
val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length)
val exceptionContext = Reg(ExceptionCause())
val pipelineHasException = exceptionValids.orR
val pipelineHasException = exceptionValids.orR //TODO FMAX maybe could be partialy pipelined
pipelineLiberator.enable setWhen(pipelineHasException)

125
src/test/cpp/regression/fail.gtkw
View File

@ -1,110 +1,47 @@
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Sun Apr 23 20:40:44 2017
[*] Sun May 28 13:48:58 2017
[*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/dhrystoneO3_Stall.vcd"
[dumpfile_mtime] "Sun Apr 23 20:39:06 2017"
[dumpfile_size] 524533821
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/fail.gtkw"
[timestart] 122461
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/regression/debugPluginExternal.vcd"
[dumpfile_mtime] "Sun May 28 12:59:45 2017"
[dumpfile_size] 905973760
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/regression/fail.gtkw"
[timestart] 1181704
[size] 1776 953
[pos] -775 -353
*-7.000000 122712 59602 124439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] -1 -353
*-6.000000 1181914 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.VexRiscv.
[sst_width] 201
[signals_width] 565
[signals_width] 392
[sst_expanded] 1
[sst_vpaned_height] 253
@28
TOP.VexRiscv.writeBack_arbitration_isValid
TOP.VexRiscv.writeBack_arbitration_isFiring
[sst_vpaned_height] 279
@22
TOP.VexRiscv.writeBack_PC[31:0]
TOP.VexRiscv.writeBack_INSTRUCTION[31:0]
TOP.VexRiscv.DebugPlugin_busReadDataReg[31:0]
@28
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_valid
TOP.VexRiscv.DebugPlugin_firstCycle
TOP.VexRiscv.DebugPlugin_haltIt
TOP.VexRiscv.DebugPlugin_haltedByBreak
TOP.VexRiscv.DebugPlugin_insertDecodeInstruction
TOP.VexRiscv.DebugPlugin_isPipActive
TOP.VexRiscv.DebugPlugin_isPipBusy
TOP.VexRiscv.DebugPlugin_resetIt
TOP.VexRiscv.DebugPlugin_stepIt
TOP.VexRiscv.debugReset
@22
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0]
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0]
TOP.VexRiscv.debug_bus_cmd_payload_address[7:0]
TOP.VexRiscv.debug_bus_cmd_payload_data[31:0]
@28
TOP.VexRiscv.execute_arbitration_isValid
TOP.VexRiscv.execute_arbitration_isStuck
@22
TOP.VexRiscv.execute_PC[31:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_isValid
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_address[31:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_wr
@800200
-execute
TOP.VexRiscv.debug_bus_cmd_payload_wr
@29
TOP.VexRiscv.dataCache_1.io_cpu_execute_isValid
TOP.VexRiscv.debug_bus_cmd_ready
@28
TOP.VexRiscv.debug_bus_cmd_valid
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_address[31:0]
TOP.VexRiscv.debug_bus_rsp_data[31:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_all
@29
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_bypass
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_data[31:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_kind[1:0]
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_mask[3:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_wr
TOP.VexRiscv.dataCache_1.io_cpu_execute_isStuck
@1000200
-execute
@28
TOP.VexRiscv.dataCache_1.io_cpu_memory_isStuck
@800200
-writeBack
@22
TOP.VexRiscv.dataCache_1.io_cpu_writeBack_data[31:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_writeBack_haltIt
TOP.VexRiscv.dataCache_1.io_cpu_writeBack_isStuck
TOP.VexRiscv.dataCache_1.io_cpu_writeBack_isValid
@1000200
-writeBack
@28
TOP.VexRiscv.dataCache_1.io_mem_cmd_valid
TOP.VexRiscv.dataCache_1.io_mem_cmd_ready
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_wr
@22
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_address[31:0]
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_data[31:0]
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_mask[3:0]
TOP.VexRiscv.dataCache_1.io_mem_rsp_payload_data[31:0]
@28
TOP.VexRiscv.dataCache_1.io_mem_rsp_valid
@22
TOP.VexRiscv.dataCache_1.dataWriteCmd_payload_data[31:0]
TOP.VexRiscv.dataCache_1.dataWriteCmd_payload_mask[3:0]
@28
TOP.VexRiscv.dataCache_1.dataWriteCmd_valid
TOP.VexRiscv.dataCache_1.clk
TOP.VexRiscv.dataCache_1.way_dataReadRspTwoEnable
@22
TOP.VexRiscv.dataCache_1.way_dataReadRspTwo[31:0]
@28
TOP.VexRiscv.dataCache_1.way_tagReadRspTwoEnable
TOP.VexRiscv.dataCache_1.way_tagReadRspTwo_dirty
TOP.VexRiscv.dataCache_1.way_tagReadRspTwo_used
@22
TOP.VexRiscv.dataCache_1.way_dataReadRspOne[31:0]
@28
TOP.VexRiscv.dataCache_1.victim_request_ready
TOP.VexRiscv.dataCache_1.victim_request_valid
TOP.VexRiscv.dataCache_1.victim_dataReadRestored
@22
TOP.VexRiscv.dataCache_1.victim_readLineCmdCounter[3:0]
TOP.VexRiscv.dataCache_1.dataReadCmd_payload[4:0]
@28
TOP.VexRiscv.dataCache_1.dataReadCmd_valid
TOP.VexRiscv.debug_resetOut
TOP.VexRiscv.decode_LEGAL_INSTRUCTION
TOP.VexRiscv.CsrPlugin_exception
TOP.VexRiscv.clk
[pattern_trace] 1
[pattern_trace] 0

75
src/test/cpp/regression/main.cpp
View File

@ -360,6 +360,7 @@ public:
}
allowedCycles-=1.0;
#ifndef REF_TIME
mTime = i/2;
#endif
@ -628,6 +629,7 @@ public:
#include <string.h>
#include <arpa/inet.h>
#include <fcntl.h>
#include <sys/ioctl.h>
/** Returns true on success, or false if there was an error */
bool SetSocketBlockingEnabled(int fd, bool blocking)
@ -722,6 +724,7 @@ public:
}
bool readRsp = false;
bool wasReady = false;
virtual void preCycle(){
if(clientHandle == -1){
clientHandle = accept(serverSocket, (struct sockaddr *) &serverStorage, &addr_size);
@ -740,11 +743,14 @@ public:
readRsp = false;
}
wasReady = top->debug_bus_cmd_ready;
}
virtual void postCycle(){
top->reset = top->debug_resetOut;
if(top->debug_bus_cmd_ready){
if(wasReady){
if(top->debug_bus_cmd_valid)
timeSpacer = 50;
top->debug_bus_cmd_valid = 0;
top->debug_bus_cmd_payload_wr = VL_RANDOM_I(1);
top->debug_bus_cmd_payload_address = VL_RANDOM_I(8);
@ -754,33 +760,41 @@ public:
if(clientHandle != -1 && top->debug_bus_cmd_valid == 0){
if(timeSpacer == 0){
int requiredSize = 1 + 1 + 4 + 4;
int n = read(clientHandle,buffer,requiredSize);
if(n == requiredSize){
bool wr = buffer[0];
uint32_t size = buffer[1];
uint32_t address = *((uint32_t*)(buffer + 2));
uint32_t data = *((uint32_t*)(buffer + 6));
if((address & ~ 0x4) == 0xFFF00000){
assert(size == 2);
top->debug_bus_cmd_valid = 1;
top->debug_bus_cmd_payload_wr = wr;
top->debug_bus_cmd_payload_address = address;
top->debug_bus_cmd_payload_data = data;
timeSpacer = 50;
int n;
if(ioctl(clientHandle,FIONREAD,&n) != 0){
connectionReset();
} else if(n >= requiredSize){
if(requiredSize != read(clientHandle,buffer,requiredSize)){
connectionReset();
} else {
bool dummy;
printf("wr=%d size=%d address=%x data=%x\n",wr,size,address,data);
ws->dBusAccess(address,wr,size,0xFFFFFFFF, &data, &dummy);
if(!wr){
if(-1 == send(clientHandle,&data,4,0)) connectionReset();
bool wr = buffer[0];
uint32_t size = buffer[1];
uint32_t address = *((uint32_t*)(buffer + 2));
uint32_t data = *((uint32_t*)(buffer + 6));
if((address & ~ 0x4) == 0xFFF00000){
assert(size == 2);
top->debug_bus_cmd_valid = 1;
top->debug_bus_cmd_payload_wr = wr;
top->debug_bus_cmd_payload_address = address;
top->debug_bus_cmd_payload_data = data;
} else {
bool dummy;
printf("wr=%d size=%d address=%x data=%x\n",wr,size,address,data);
ws->dBusAccess(address,wr,size,0xFFFFFFFF, &data, &dummy);
if(!wr){
if(-1 == send(clientHandle,&data,4,0)) connectionReset();
}
}
}
} else {
connectionReset();
int error = 0;
socklen_t len = sizeof (error);
int retval = getsockopt (clientHandle, SOL_SOCKET, SO_ERROR, &error, &len);
if (retval != 0 || error != 0) {
connectionReset();
}
}
} else {
timeSpacer--;
@ -1195,7 +1209,16 @@ int main(int argc, char **argv, char **env) {
#ifndef REF
#ifdef DEBUG_PLUGIN_EXTERNAL
Workspace("debugPluginExternal").loadHex("../../resources/hex/debugPluginExternal.hex")->noInstructionReadCheck()->setCyclesPerSecond(5e3)->run(1e9);
{
Workspace w("debugPluginExternal");
w.loadHex("../../resources/hex/debugPluginExternal.hex");
w.noInstructionReadCheck();
#if defined(TRACE) || defined(TRACE_ACCESS)
//w.setCyclesPerSecond(5e3);
printf("Speed reduced 5Khz\n");
#endif
w.run(1e9);
}
#endif
@ -1233,7 +1256,7 @@ int main(int argc, char **argv, char **env) {
#endif
#ifdef DEBUG_PLUGIN
redo(REDO,DebugPluginTest().run(100e3););
redo(REDO,DebugPluginTest().run(1e6););
#endif
#ifdef DHRYSTONE

4
src/test/cpp/regression/makefile
View File

@ -1,12 +1,12 @@
IBUS=IBUS_SIMPLE
DBUS=DBUS_SIMPLE
TRACE?=no
TRACE_ACCESS=no
TRACE_ACCESS?=no
TRACE_START=0
CSR=yes
MMU=yes
DEBUG_PLUGIN=yes
DEBUG_PLUGIN_EXTERNAL=yes
DEBUG_PLUGIN_EXTERNAL?=no
DHRYSTONE=yes
FREE_RTOS=no
REDO=10