also need to expose privilege state

turns out SATP is not enough to figure out what code you're running,
because the kernel code is mapped into all userspace's virtual memory
areas. You also need the privilege state to be exported.

This creates an option to export those bits.

src/main/scala/vexriscv/plugin/CsrPlugin.scala

@@ -82,6 +82,7 @@ case class CsrPluginConfig(
                             deterministicInteruptionEntry : Boolean = false, //Only used for simulatation purposes
                             wfiOutput           : Boolean = false,
                             withPrivilegedDebug : Boolean = false, //For the official RISC-V debug spec implementation
+                            exportPrivilege     : Boolean = false,
                             var debugTriggers       : Int     = 2
                           ){
   assert(!ucycleAccess.canWrite)
@@ -612,6 +613,9 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
     contextSwitching = Bool().setName("contextSwitching")
 
     privilege = UInt(2 bits).setName("CsrPlugin_privilege")
+    if (exportPrivilege) {
+      val export_priv = out(privilege)
+    }
     forceMachineWire = False
 
     if(catchIllegalAccess || ecallGen || withEbreak)