Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

also need to expose privilege state 

turns out SATP is not enough to figure out what code you're running,
because the kernel code is mapped into all userspace's virtual memory
areas. You also need the privilege state to be exported.

This creates an option to export those bits.
This commit is contained in:
buncram 2023-01-16 02:16:25 +08:00
parent 11f391eadf
commit 2297f8aea0
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -82,6 +82,7 @@ case class CsrPluginConfig(
deterministicInteruptionEntry : Boolean = false, //Only used for simulatation purposes deterministicInteruptionEntry : Boolean = false, //Only used for simulatation purposes
wfiOutput : Boolean = false, wfiOutput : Boolean = false,
withPrivilegedDebug : Boolean = false, //For the official RISC-V debug spec implementation withPrivilegedDebug : Boolean = false, //For the official RISC-V debug spec implementation
exportPrivilege : Boolean = false,
var debugTriggers : Int = 2 var debugTriggers : Int = 2
){ ){
assert(!ucycleAccess.canWrite) assert(!ucycleAccess.canWrite)
@ -612,6 +613,9 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
contextSwitching = Bool().setName("contextSwitching") contextSwitching = Bool().setName("contextSwitching")
privilege = UInt(2 bits).setName("CsrPlugin_privilege") privilege = UInt(2 bits).setName("CsrPlugin_privilege")
if (exportPrivilege) {
val export_priv = out(privilege)
}
forceMachineWire = False forceMachineWire = False
if(catchIllegalAccess || ecallGen || withEbreak) if(catchIllegalAccess || ecallGen || withEbreak)