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VexRiscv
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Add RVC into the readme 

Forgot to add RVC (compressed) support information into the readme
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README.md
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@ -26,7 +26,7 @@
This repository hosts a RISC-V implementation written in SpinalHDL. Here are some specs : This repository hosts a RISC-V implementation written in SpinalHDL. Here are some specs :
- RV32I[M] instruction set - RV32I[M][C] instruction set
- Pipelined with 5 stages (Fetch, Decode, Execute, Memory, WriteBack) - Pipelined with 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
- 1.44 DMIPS/Mhz when all features are enabled - 1.44 DMIPS/Mhz when all features are enabled
- Optimized for FPGA, fully portable - Optimized for FPGA, fully portable