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VexRiscv
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update Riscv software model lrsc implementation

This commit is contained in:
Charles Papon 2019-04-23 21:55:07 +02:00
parent 4078f84e8f
commit 266bdccc2e
1 changed files with 9 additions and 18 deletions
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27
src/test/cpp/regression/main.cpp
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@ -374,14 +374,8 @@ public:
}; };
}; };
#define RESERVED_ENTRY_COUNT 1
struct ReservedEntry{
bool valid;
uint32_t address;
};
ReservedEntry reservedEntries[RESERVED_ENTRY_COUNT]; bool lrscReserved;
int reservedEntriesPtr = 0;
RiscvGolden() { RiscvGolden() {
pc = 0x80000000; pc = 0x80000000;
@ -389,9 +383,6 @@ public:
for (int i = 0; i < 32; i++) for (int i = 0; i < 32; i++)
regs[i] = 0; regs[i] = 0;
for(int i = 0;i < RESERVED_ENTRY_COUNT;i++) reservedEntries[i].valid = false;
status.raw = 0; status.raw = 0;
ie.raw = 0; ie.raw = 0;
mtvec.raw = 0x80000020; mtvec.raw = 0x80000020;
@ -409,6 +400,7 @@ public:
ipSoft = 0; ipSoft = 0;
ipInput = 0; ipInput = 0;
stepCounter = 0; stepCounter = 0;
lrscReserved = false;
} }
virtual void rfWrite(int32_t address, int32_t data) { virtual void rfWrite(int32_t address, int32_t data) {
@ -472,7 +464,7 @@ public:
cout << hex << " a7=0x" << regs[17] << " a0=0x" << regs[10] << " a1=0x" << regs[11] << " a2=0x" << regs[12] << dec << endl; cout << hex << " a7=0x" << regs[17] << " a0=0x" << regs[10] << " a1=0x" << regs[11] << " a2=0x" << regs[12] << dec << endl;
} }
#endif #endif
for(int i = 0;i < RESERVED_ENTRY_COUNT;i++) reservedEntries[i].valid = false; lrscReserved = false;
//Check leguality of the interrupt //Check leguality of the interrupt
if(interrupt) { if(interrupt) {
bool hit = false; bool hit = false;
@ -843,6 +835,7 @@ public:
status.mpie = 1; status.mpie = 1;
status.mpp = 0; status.mpp = 0;
pcWrite(mepc); pcWrite(mepc);
lrscReserved = false;
}break; }break;
case 0x10200073:{ //SRET case 0x10200073:{ //SRET
if(privilege < 1){ ilegalInstruction(); return;} if(privilege < 1){ ilegalInstruction(); return;}
@ -851,6 +844,7 @@ public:
status.spie = 1; status.spie = 1;
status.spp = 0; status.spp = 0;
pcWrite(sepc); pcWrite(sepc);
lrscReserved = false;
}break; }break;
case 0x00000073:{ //ECALL case 0x00000073:{ //ECALL
trap(0, 8+privilege, 0x00000073); //To follow the VexRiscv area saving implementation trap(0, 8+privilege, 0x00000073); //To follow the VexRiscv area saving implementation
@ -899,9 +893,7 @@ public:
if(dRead(pAddr, 4, &data)){ if(dRead(pAddr, 4, &data)){
trap(0, 5, address); trap(0, 5, address);
} else { } else {
reservedEntries[reservedEntriesPtr].valid = true; lrscReserved = true;
reservedEntries[reservedEntriesPtr].address = address;
reservedEntriesPtr = (reservedEntriesPtr + 1) % RESERVED_ENTRY_COUNT;
rfWrite(rd32, data); rfWrite(rd32, data);
pcWrite(pc + 4); pcWrite(pc + 4);
} }
@ -913,8 +905,7 @@ public:
trap(0, 6, address); trap(0, 6, address);
} else { } else {
if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; } if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
bool hit = false; bool hit = lrscReserved;
for(int i = 0;i < RESERVED_ENTRY_COUNT;i++) hit |= reservedEntries[i].valid && reservedEntries[i].address == address;
if(hit){ if(hit){
dWrite(pAddr, 4, i32_rs2); dWrite(pAddr, 4, i32_rs2);
} }
@ -3762,11 +3753,11 @@ int main(int argc, char **argv, char **env) {
#ifdef LRSC #ifdef LRSC
redo(REDO,WorkspaceRegression("lrsc").loadHex("../raw/lrsc/build/lrsc.hex")->bootAt(0x00000000u)->run(10e3);); redo(REDO,WorkspaceRegression("lrsc").withRiscvRef()->loadHex("../raw/lrsc/build/lrsc.hex")->bootAt(0x00000000u)->run(10e3););
#endif #endif
#ifdef AMO #ifdef AMO
redo(REDO,WorkspaceRegression("amo").loadHex("../raw/amo/build/amo.hex")->bootAt(0x00000000u)->run(10e3);); redo(REDO,WorkspaceRegression("amo").withRiscvRef()->loadHex("../raw/amo/build/amo.hex")->bootAt(0x00000000u)->run(10e3););
#endif #endif
#ifdef DHRYSTONE #ifdef DHRYSTONE