Decoding logic : Add primes duplication removal
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Dolu1990
parent
2b6f43cef8
commit
2b6185b063
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@ -17,6 +17,7 @@ import spinal.lib.eda.altera.{ResetEmitterTag, InterruptReceiverTag, QSysify}
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//
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//}
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//make clean run DBUS=CACHED_AVALON IBUS=CACHED_AVALON MMU=no CSR=no DEBUG_PLUGIN=AVALON
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object VexRiscvAvalonForSim{
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def main(args: Array[String]) {
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@ -26,51 +27,51 @@ object VexRiscvAvalonForSim{
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val cpuConfig = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, false),
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// new IBusSimplePlugin(
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// interfaceKeepData = false,
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// catchAccessFault = false
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// ),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = false,
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// catchAccessFault = false
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// ),
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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catchMemoryTranslationMiss = true,
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asyncTagMemory = false,
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twoCycleRam = true
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)
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// askMemoryTranslation = true,
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 4
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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// new IBusCachedPlugin(
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// config = InstructionCacheConfig(
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// cacheSize = 4096,
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// bytePerLine =32,
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// wayCount = 1,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchIllegalAccess = true,
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// catchAccessFault = true,
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// catchMemoryTranslationMiss = true,
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// asyncTagMemory = false,
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// twoCycleRam = true
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// )
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),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true,
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catchMemoryTranslationMiss = true
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),
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memoryTranslatorPortConfig = null
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 6
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// )
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),
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// // askMemoryTranslation = true,
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// // memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// // portTlbSize = 4
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// // )
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// ),
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// new DBusCachedPlugin(
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// config = new DataCacheConfig(
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// cacheSize = 4096,
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// bytePerLine = 32,
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// wayCount = 1,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchAccessError = true,
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// catchIllegal = true,
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// catchUnaligned = true,
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// catchMemoryTranslationMiss = true
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// ),
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// memoryTranslatorPortConfig = null
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// // memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// // portTlbSize = 6
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// // )
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// ),
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new StaticMemoryTranslatorPlugin(
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ioRange = _(31 downto 28) === 0xF
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),
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@ -204,15 +204,17 @@ object SymplifyBit{
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if (term.value.testBit(i))
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t = Masked(term.value.clearBit(i), term.care)
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}
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if (t != null && !falseTerms.exists(_.intersects(t)))
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if (t != null && !falseTerms.exists(_.intersects(t))) {
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t.isPrime = false
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return t
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}
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}
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null
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}
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//Return primes implicants for the trueTerms, falseTerms spec. Default value is don't care
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def getPrimeImplicantsByTrueAndFalse(trueTerms: Seq[Masked], falseTerms: Seq[Masked], inputWidth : Int): Seq[Masked] = {
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val primes = ArrayBuffer[Masked]()
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val primes = mutable.LinkedHashSet[Masked]()
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trueTerms.foreach(_.isPrime = true)
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falseTerms.foreach(_.isPrime = true)
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val trueTermByCareCount = (inputWidth to 0 by -1).map(b => trueTerms.filter(b == _.care.bitCount))
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@ -243,29 +245,44 @@ object SymplifyBit{
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primes += p
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}
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verify(primes, trueTerms, falseTerms)
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def optimise() {
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val duplicateds = primes.filter(prime => verifyTrueFalse(primes.filterNot(_ == prime), trueTerms, falseTerms))
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if(duplicateds.nonEmpty) {
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primes -= duplicateds.maxBy(_.care.bitCount)
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optimise()
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}
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}
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optimise()
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verifyTrueFalse(primes, trueTerms, falseTerms)
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var duplication = 0
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for(prime <- primes){
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try{
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verify(primes.filterNot(_ == prime), trueTerms, falseTerms)
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assert(false)
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} catch {
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case _ : Throwable =>
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if(verifyTrueFalse(primes.filterNot(_ == prime), trueTerms, falseTerms)){
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duplication += 1
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}
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}
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primes
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if(duplication != 0){
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PendingError(s"Duplicated primes : $duplication")
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}
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primes.toSeq
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}
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//Verify that the 'terms' doesn't violate the trueTerms ++ falseTerms spec
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def verify(terms : Seq[Masked], trueTerms : Seq[Masked], falseTerms : Seq[Masked]): Unit ={
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require(trueTerms.forall(trueTerm => terms.exists(_ covers trueTerm)))
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require(falseTerms.forall(falseTerm => !terms.exists(_ covers falseTerm)))
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def verifyTrueFalse(terms : Iterable[Masked], trueTerms : Seq[Masked], falseTerms : Seq[Masked]): Boolean ={
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return (trueTerms.forall(trueTerm => terms.exists(_ covers trueTerm))) && (falseTerms.forall(falseTerm => !terms.exists(_ covers falseTerm)))
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}
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def checkTrue(terms : Iterable[Masked], trueTerms : Seq[Masked]): Boolean ={
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return trueTerms.forall(trueTerm => terms.exists(_ covers trueTerm))
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}
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// Return primes implicants for the trueTerms, default value is False.
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// You can insert don't care values by adding non-prime implicants in the trueTerms
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// Will simplify the trueTerms from the most constrained ones to the least constrained ones
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def getPrimeImplicantsByTrueAndDontCare(trueTerms: Seq[Masked],dontCareTerms: Seq[Masked], inputWidth : Int): Seq[Masked] = {
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val primes = ArrayBuffer[Masked]()
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val primes = mutable.LinkedHashSet[Masked]()
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trueTerms.foreach(_.isPrime = true)
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dontCareTerms.foreach(_.isPrime = false)
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val termsByCareCount = (inputWidth to 0 by -1).map(b => (trueTerms ++ dontCareTerms).filter(b == _.care.bitCount))
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@ -281,7 +298,29 @@ object SymplifyBit{
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for (p <- r; if p.isPrime)
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primes += p
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}
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primes
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def optimise() {
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val duplicateds = primes.filter(prime => checkTrue(primes.filterNot(_ == prime), trueTerms))
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if(duplicateds.nonEmpty) {
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primes -= duplicateds.maxBy(_.care.bitCount)
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optimise()
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}
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}
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optimise()
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var duplication = 0
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for(prime <- primes){
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if(checkTrue(primes.filterNot(_ == prime), trueTerms)){
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duplication += 1
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}
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}
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if(duplication != 0){
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PendingError(s"Duplicated primes : $duplication")
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}
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primes.toSeq
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}
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def main(args: Array[String]) {
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@ -303,11 +342,11 @@ object SymplifyBit{
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println("UUT")
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println(reducedPrimeImplicants.map(_.toString(4)).mkString("\n"))
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}
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// {
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// val trueTerms = List(0, 15).map(v => Masked(v, 0xF))
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// val falseTerms = List(3).map(v => Masked(v, 0xF))
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// val primes = getPrimeImplicants(trueTerms, falseTerms, 4)
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// println(primes.map(_.toString(4)).mkString("\n"))
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// }
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{
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val trueTerms = List(0, 15).map(v => Masked(v, 0xF))
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val falseTerms = List(3).map(v => Masked(v, 0xF))
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val primes = getPrimeImplicantsByTrueAndFalse(trueTerms, falseTerms, 4)
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println(primes.map(_.toString(4)).mkString("\n"))
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}
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}
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}
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