Fix Murax memory mapping range
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@ -278,7 +278,7 @@ case class Murax(config : MuraxConfig) extends Component{
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val logic = new MuraxSimpleBusDecoder(
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master = mainBusArbiter.io.masterBus,
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specification = List[(SimpleBus,SizeMapping)](
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ram.io.bus -> (0x80000000l, onChipRamSize kB),
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ram.io.bus -> (0x80000000l, onChipRamSize),
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apbBridge.io.simpleBus -> (0xF0000000l, 1 MB)
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),
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pipelineMaster = pipelineMainBus
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