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Fix Murax memory mapping range

This commit is contained in:
Dolu1990 2018-02-23 19:16:31 +01:00
parent 5260ad5c35
commit 2b6f43cef8
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/vexriscv/demo/Murax.scala
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@ -278,7 +278,7 @@ case class Murax(config : MuraxConfig) extends Component{
val logic = new MuraxSimpleBusDecoder( val logic = new MuraxSimpleBusDecoder(
master = mainBusArbiter.io.masterBus, master = mainBusArbiter.io.masterBus,
specification = List[(SimpleBus,SizeMapping)]( specification = List[(SimpleBus,SizeMapping)](
ram.io.bus -> (0x80000000l, onChipRamSize kB), ram.io.bus -> (0x80000000l, onChipRamSize),
apbBridge.io.simpleBus -> (0xF0000000l, 1 MB) apbBridge.io.simpleBus -> (0xF0000000l, 1 MB)
), ),
pipelineMaster = pipelineMainBus pipelineMaster = pipelineMainBus