Fix Murax memory mapping range

2018-02-23 19:16:31 +01:00 · 2018-02-23 19:16:31 +01:00 · 2b6f43cef8
parent 5260ad5c35
commit 2b6f43cef8
1 changed files with 1 additions and 1 deletions
--- a/src/main/scala/vexriscv/demo/Murax.scala
+++ b/src/main/scala/vexriscv/demo/Murax.scala
@ -278,7 +278,7 @@ case class Murax(config : MuraxConfig) extends Component{
      val logic = new MuraxSimpleBusDecoder(
        master = mainBusArbiter.io.masterBus,
        specification = List[(SimpleBus,SizeMapping)](
-          ram.io.bus             -> (0x80000000l, onChipRamSize kB),
+          ram.io.bus             -> (0x80000000l, onChipRamSize),
          apbBridge.io.simpleBus -> (0xF0000000l, 1 MB)
        ),
        pipelineMaster = pipelineMainBus