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Fix DBus AXI bridges from writePending counter deadlock

This commit is contained in:
Charles Papon 2019-11-03 16:43:29 +01:00
parent bd2787b562
commit 2bf6a536c9
2 changed files with 12 additions and 9 deletions
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9
src/main/scala/vexriscv/ip/DataCache.scala
View File

@ -184,16 +184,17 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
slave(rsp) slave(rsp)
} }
def toAxi4Shared(stageCmd : Boolean = false): Axi4Shared = { def toAxi4Shared(stageCmd : Boolean = false, pendingWritesMax : Int = 7): Axi4Shared = {
val axi = Axi4Shared(p.getAxi4SharedConfig()) val axi = Axi4Shared(p.getAxi4SharedConfig())
val pendingWritesMax = 7
val cmdPreFork = if (stageCmd) cmd.stage.stage().s2mPipe() else cmd
val pendingWrites = CounterUpDown( val pendingWrites = CounterUpDown(
stateCount = pendingWritesMax + 1, stateCount = pendingWritesMax + 1,
incWhen = axi.sharedCmd.fire && axi.sharedCmd.write, incWhen = cmdPreFork.fire && cmdPreFork.wr,
decWhen = axi.writeRsp.fire decWhen = axi.writeRsp.fire
) )
val cmdPreFork = if (stageCmd) cmd.stage.stage().s2mPipe() else cmd
val hazard = (pendingWrites =/= 0 && !cmdPreFork.wr) || pendingWrites === pendingWritesMax val hazard = (pendingWrites =/= 0 && !cmdPreFork.wr) || pendingWrites === pendingWritesMax
val (cmdFork, dataFork) = StreamFork2(cmdPreFork.haltWhen(hazard)) val (cmdFork, dataFork) = StreamFork2(cmdPreFork.haltWhen(hazard))
val cmdStage = cmdFork.throwWhen(RegNextWhen(!cmdFork.last,cmdFork.fire).init(False)) val cmdStage = cmdFork.throwWhen(RegNextWhen(!cmdFork.last,cmdFork.fire).init(False))

12
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
View File

@ -106,17 +106,19 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
s s
} }
def toAxi4Shared(stageCmd : Boolean = false): Axi4Shared = { def toAxi4Shared(stageCmd : Boolean = false, pendingWritesMax : Int = 7): Axi4Shared = {
val axi = Axi4Shared(DBusSimpleBus.getAxi4Config()) val axi = Axi4Shared(DBusSimpleBus.getAxi4Config())
val pendingWritesMax = 7
val cmdPreFork = if (stageCmd) cmd.stage.stage().s2mPipe() else cmd
val pendingWrites = CounterUpDown( val pendingWrites = CounterUpDown(
stateCount = pendingWritesMax + 1, stateCount = pendingWritesMax + 1,
incWhen = axi.sharedCmd.fire && axi.sharedCmd.write, incWhen = cmdPreFork.fire && cmdPreFork.wr,
decWhen = axi.writeRsp.fire decWhen = axi.writeRsp.fire
) )
val cmdPreFork = if (stageCmd) cmd.stage.stage().s2mPipe() else cmd val hazard = (pendingWrites =/= 0 && cmdPreFork.valid && !cmdPreFork.wr) || pendingWrites === pendingWritesMax
val (cmdFork, dataFork) = StreamFork2(cmdPreFork.haltWhen((pendingWrites =/= 0 && cmdPreFork.valid && !cmdPreFork.wr) || pendingWrites === pendingWritesMax)) val (cmdFork, dataFork) = StreamFork2(cmdPreFork.haltWhen(hazard))
axi.sharedCmd.arbitrationFrom(cmdFork) axi.sharedCmd.arbitrationFrom(cmdFork)
axi.sharedCmd.write := cmdFork.wr axi.sharedCmd.write := cmdFork.wr
axi.sharedCmd.prot := "010" axi.sharedCmd.prot := "010"