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VexRiscv
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Add configs setup in SimpleBusInterconnect

This commit is contained in:
Dolu1990 2018-11-29 16:14:41 +01:00
parent 7075e08d9f
commit 2f6a2dfccc
4 changed files with 17 additions and 6 deletions
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11
src/main/scala/vexriscv/demo/SimpleBus.scala
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@ -228,8 +228,17 @@ case class SimpleBusInterconnect(){
val slaves = mutable.LinkedHashMap[SimpleBus, SlaveModel]() val slaves = mutable.LinkedHashMap[SimpleBus, SlaveModel]()
val connections = ArrayBuffer[ConnectionModel]() val connections = ArrayBuffer[ConnectionModel]()
var arbitrationPendingRspMaxDefault = 1 var arbitrationPendingRspMaxDefault = 1
val arbitrationRspRouteQueueDefault = false var arbitrationRspRouteQueueDefault = false
def perfConfig(): Unit ={
arbitrationPendingRspMaxDefault = 7
arbitrationRspRouteQueueDefault = true
}
def areaConfig(): Unit ={
arbitrationPendingRspMaxDefault = 1
arbitrationRspRouteQueueDefault = false
}
def setConnector(bus : SimpleBus)( connector : (SimpleBus,SimpleBus) => Unit): Unit = (masters.get(bus), slaves.get(bus)) match { def setConnector(bus : SimpleBus)( connector : (SimpleBus,SimpleBus) => Unit): Unit = (masters.get(bus), slaves.get(bus)) match {
case (Some(m), _) => m.connector = connector case (Some(m), _) => m.connector = connector

4
src/test/cpp/regression/main.cpp
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@ -685,6 +685,7 @@ public:
ws->iBusAccessPatch(address,data,&error); ws->iBusAccessPatch(address,data,&error);
} }
virtual bool dRead(int32_t address, int32_t size, uint32_t *data){ virtual bool dRead(int32_t address, int32_t size, uint32_t *data){
if(address & (size-1) != 0) cout << "Ref did a unaligned read" << endl;
if((address & 0xF0000000) == 0xF0000000){ if((address & 0xF0000000) == 0xF0000000){
MemRead t = periphRead.front(); MemRead t = periphRead.front();
if(t.address != address || t.size != size){ if(t.address != address || t.size != size){
@ -697,6 +698,7 @@ public:
} }
} }
virtual void dWrite(int32_t address, int32_t size, uint32_t data){ virtual void dWrite(int32_t address, int32_t size, uint32_t data){
if(address & (size-1) != 0) cout << "Ref did a unaligned write" << endl;
if((address & 0xF0000000) == 0xF0000000){ if((address & 0xF0000000) == 0xF0000000){
MemWrite w; MemWrite w;
w.address = address; w.address = address;
@ -1023,7 +1025,7 @@ public:
#endif #endif
if(top->VexRiscv->writeBack_arbitration_isFiring){ if(top->VexRiscv->writeBack_arbitration_isFiring){
if(riscvRefEnable && top->VexRiscv->writeBack_PC != riscvRef.pc){ if(riscvRefEnable && top->VexRiscv->writeBack_PC != riscvRef.pc){
cout << "pc missmatch" << endl; cout << " pc missmatch " << top->VexRiscv->writeBack_PC << " should be " << riscvRef.pc << endl;
fail(); fail();
} }

4
src/test/python/gcloud/run.sh
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@ -10,8 +10,8 @@ cd VexRiscv
sudo git init sudo git init
sudo git add * sudo git add *
sudo git commit -m miaou sudo git commit -m miaou
export VEXRISCV_REGRESSION_CONFIG_COUNT=64 export VEXRISCV_REGRESSION_CONFIG_COUNT=128
export VEXRISCV_REGRESSION_FREERTOS_COUNT=yes export VEXRISCV_REGRESSION_FREERTOS_COUNT=30
sbt test sbt test
cd .. cd ..

4
src/test/scala/vexriscv/TestIndividualFeatures.scala
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@ -523,8 +523,8 @@ class TestIndividualFeatures extends FunSuite {
// val testId = Some(mutable.HashSet[Int](0,28,45,93)) // val testId = Some(mutable.HashSet[Int](0,28,45,93))
// val testId = Some(mutable.HashSet[Int](9)) // val testId = Some(mutable.HashSet[Int](5))
// val seed = -8173808854505304814l // val seed = -2089952013329208578l