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VexRiscv
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unsetRegIfNoAssignement -> allowUnsetRegToAvoidLatch

This commit is contained in:
Dolu1990 2017-11-10 11:33:04 +01:00
parent c3a7f4e58c
commit 3060296b94
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -260,10 +260,10 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
//Define CSR registers //Define CSR registers
val misa = new Area{ val misa = new Area{
val base = Reg(UInt(2 bits)) init(U"01") unsetRegIfNoAssignement val base = Reg(UInt(2 bits)) init(U"01") allowUnsetRegToAvoidLatch
val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) unsetRegIfNoAssignement val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) allowUnsetRegToAvoidLatch
} }
val mtvec = RegInit(U(mtvecInit,xlen bits)) unsetRegIfNoAssignement val mtvec = RegInit(U(mtvecInit,xlen bits)) allowUnsetRegToAvoidLatch
val mepc = Reg(UInt(xlen bits)) val mepc = Reg(UInt(xlen bits))
val mstatus = new Area{ val mstatus = new Area{
val MIE, MPIE = RegInit(False) val MIE, MPIE = RegInit(False)
@ -337,7 +337,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{ val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{
val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min
val exceptionValids = Vec(Bool,stages.length) val exceptionValids = Vec(Bool,stages.length)
val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length).unsetRegIfNoAssignement val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length).allowUnsetRegToAvoidLatch
val exceptionContext = Reg(ExceptionCause()) val exceptionContext = Reg(ExceptionCause())
val pipelineHasException = exceptionValids.orR //TODO FMAX maybe could be partialy pipelined val pipelineHasException = exceptionValids.orR //TODO FMAX maybe could be partialy pipelined