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VexRiscv
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Now mret and ebreak are only allowed in CSR machine mode

This commit is contained in:
Dolu1990 2018-01-28 16:34:47 +01:00
parent 93da5d29bc
commit 307c0b6bfa
2 changed files with 14 additions and 12 deletions
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20
src/main/scala/vexriscv/TestsWorkspace.scala
View File

@ -41,7 +41,7 @@ object TestsWorkspace {
// ),
new IBusCachedPlugin(
config = InstructionCacheConfig(
cacheSize = 4096*4,
cacheSize = 4096,
bytePerLine =32,
wayCount = 1,
wrappedMemAccess = true,
@ -66,7 +66,7 @@ object TestsWorkspace {
// ),
new DBusCachedPlugin(
config = new DataCacheConfig(
cacheSize = 4096*4,
cacheSize = 4096,
bytePerLine = 32,
wayCount = 1,
addressWidth = 32,
@ -83,14 +83,14 @@ object TestsWorkspace {
portTlbSize = 6
)
),
new StaticMemoryTranslatorPlugin(
ioRange = _(31 downto 28) === 0xF
),
// new MemoryTranslatorPlugin(
// tlbSize = 32,
// virtualRange = _(31 downto 28) === 0xC,
// new StaticMemoryTranslatorPlugin(
// ioRange = _(31 downto 28) === 0xF
// ),
new MemoryTranslatorPlugin(
tlbSize = 32,
virtualRange = _(31 downto 28) === 0xC,
ioRange = _(31 downto 28) === 0xF
),
new DecoderSimplePlugin(
catchIllegalInstruction = true
),
@ -102,7 +102,7 @@ object TestsWorkspace {
new SrcPlugin(
separatedAddSub = false
),
new FullBarrielShifterPlugin(earlyInjection = true),
new FullBarrielShifterPlugin(earlyInjection = false),
// new LightShifterPlugin,
new HazardSimplePlugin(
bypassExecute = true,
@ -120,7 +120,7 @@ object TestsWorkspace {
new CsrPlugin(CsrPluginConfig.all),
new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
new BranchPlugin(
earlyBranch = true,
earlyBranch = false,
catchAddressMisaligned = true,
prediction = DYNAMIC
),

6
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -452,9 +452,11 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
execute plug new Area {
import execute._
val illegalAccess = True
val illegalAccess = arbitration.isValid && input(IS_CSR)
if(catchIllegalAccess) {
selfException.valid := arbitration.isValid && input(IS_CSR) && illegalAccess
val illegalInstruction = arbitration.isValid && privilege === 0 && (input(ENV_CTRL) === EnvCtrlEnum.EBREAK || input(ENV_CTRL) === EnvCtrlEnum.MRET)
selfException.valid := illegalAccess || illegalInstruction
selfException.code := 2
selfException.badAddr.assignDontCare()
}