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VexRiscv now pass Riscv-test compressed stuff

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This commit is contained in:
Dolu1990 2018-03-21 20:50:07 +01:00
parent af638e7bde
commit 31a464ffdc
3 changed files with 6 additions and 5 deletions
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4
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View file

@ -236,7 +236,7 @@ object RvcDecompressor{
val addJ = (i(6 downto 2) === 0) ? j | add
ret := (i(12 downto 2) === B"100_0000_0000") ? ebreak | addJ
}
is(22){ ret := swspImm(11 downto 5) ## i(6 downto 2) ## x2 ## B"010" ## swImm(4 downto 0) ## B"0100011" }
is(22){ ret := swspImm(11 downto 5) ## i(6 downto 2) ## x2 ## B"010" ## swspImm(4 downto 0) ## B"0100011" }
}
ret
@ -418,7 +418,7 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
bufferValid clearWhen(output.fire)
when(input.ready){
when(input.valid) {
bufferValid := !(!isRvc && !input.pc(1) && !bufferValid)
bufferValid := !(!isRvc && !input.pc(1) && !bufferValid) && !(isRvc && input.pc(1))
}
bufferData := input.rsp.inst(31 downto 16)
}

5
src/test/cpp/regression/main.cpp
View file

@ -1333,11 +1333,12 @@ public:
iBusAccess(top->VexRiscv->writeBack_PC, &instruction, &error);
if(instruction == 0x00000073){
uint32_t code = top->VexRiscv->RegFilePlugin_regFile[28];
if((code & 1) == 0){
uint32_t code2 = top->VexRiscv->RegFilePlugin_regFile[3];
if((code & 1) == 0 && (code2 & 1) == 0){
cout << "Wrong error code"<< endl;
fail();
}
if(code == 1){
if(code == 1 || code2 == 1){
pass();
}else{
cout << "Error code " << code/2 << endl;

2
src/test/python/tool/disasm.s
View file

@ -1 +1 @@
.word 0xf47413
.word 0x301c63