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VexRiscv
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Fix performance of removed instruction which halt were halting the pipeline

This commit is contained in:
Charles Papon 2017-03-18 10:51:55 +01:00
parent 20ca348707
commit 31db6511dc
3 changed files with 74 additions and 4 deletions
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4
src/main/scala/SpinalRiscv/Pipeline.scala
View File

@ -92,7 +92,7 @@ trait Pipeline {
inputDefault := stage.inserts(key)
} else {
val stageBefore = stages(stageIndex - 1)
inputDefault := RegNextWhen(stageBefore.output(key), !stage.arbitration.isStuck) //!stage.input.valid || stage.input.ready
inputDefault := RegNextWhen(stageBefore.output(key), !stage.arbitration.isStuck || stage.arbitration.removeIt)
}
}
}
@ -100,7 +100,7 @@ trait Pipeline {
//Arbitration
for(stageIndex <- 0 until stages.length; stage = stages(stageIndex)){
stage.arbitration.isStuckByOthers := stages.takeRight(stages.length - stageIndex - 1).map(_.arbitration.haltIt).foldLeft(False)(_ || _)
stage.arbitration.isStuckByOthers := stages.takeRight(stages.length - stageIndex - 1).map(s => s.arbitration.haltIt && !s.arbitration.removeIt).foldLeft(False)(_ || _)
stage.arbitration.isStuck := stage.arbitration.haltIt || stage.arbitration.isStuckByOthers
stage.arbitration.isFiring := stage.arbitration.isValid && !stage.arbitration.isStuck && !stage.arbitration.removeIt
}

12
src/test/cpp/testA/main.cpp
View File

@ -212,7 +212,11 @@ public:
uint32_t addr = top->dCmd_payload_address;
if(top->dCmd_payload_wr){
memTraces << currentTime << " : WRITE mem" << (1 << top->dCmd_payload_size) << "[" << addr << "] = " << top->dCmd_payload_data << endl;
memTraces << (currentTime
#ifdef REF
-2
#endif
) << " : WRITE mem" << (1 << top->dCmd_payload_size) << "[" << addr << "] = " << top->dCmd_payload_data << endl;
for(uint32_t b = 0;b < (1 << top->dCmd_payload_size);b++){
uint32_t offset = (addr+b)&0x3;
*mem.get(addr + b) = top->dCmd_payload_data >> (offset*8);
@ -234,7 +238,11 @@ public:
dRsp_inst_next = i/2;
break;
}
memTraces << currentTime << " : READ mem" << (1 << top->dCmd_payload_size) << "[" << addr << "] = " << dRsp_inst_next << endl;
memTraces << (currentTime
#ifdef REF
-2
#endif
) << " : READ mem" << (1 << top->dCmd_payload_size) << "[" << addr << "] = " << dRsp_inst_next << endl;
}
}

62
src/test/cpp/testA/wrongDiff.gtkw Normal file
View File

@ -0,0 +1,62 @@
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Sat Mar 18 09:49:22 2017
[*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/DhrystoneWrong.vcd"
[dumpfile_mtime] "Sat Mar 18 08:08:53 2017"
[dumpfile_size] 1450277049
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/wrongDiff.gtkw"
[timestart] 37402
[size] 1774 476
[pos] -1 475
*-2.000000 37407 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.VexRiscv.
[sst_width] 201
[signals_width] 583
[sst_expanded] 1
[sst_vpaned_height] 112
@28
TOP.VexRiscv.fetch_arbitration_isStuck
TOP.VexRiscv.decode_arbitration_isStuck
TOP.VexRiscv.execute_arbitration_isStuck
TOP.VexRiscv.memory_arbitration_isStuck
TOP.VexRiscv.writeBack_arbitration_isStuck
TOP.VexRiscv.prefetch_arbitration_isValid
TOP.VexRiscv.fetch_arbitration_isValid
@29
TOP.VexRiscv.decode_arbitration_isValid
@28
TOP.VexRiscv.execute_arbitration_isValid
TOP.VexRiscv.memory_arbitration_isValid
TOP.VexRiscv.writeBack_arbitration_isValid
@22
TOP.VexRiscv.writeBack_input_PC[31:0]
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0]
@24
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0]
@28
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_valid
TOP.VexRiscv.writeBack_arbitration_isValid
TOP.VexRiscv.clk
TOP.dCmd_valid
TOP.dCmd_ready
TOP.dCmd_payload_wr
TOP.dCmd_payload_size[1:0]
@22
TOP.dCmd_payload_address[31:0]
TOP.dCmd_payload_data[31:0]
@24
TOP.dRsp_data[31:0]
@22
TOP.VexRiscv.execute_input_PC[31:0]
TOP.VexRiscv.execute_input_INSTRUCTION[31:0]
@28
TOP.VexRiscv.fetch_arbitration_removeIt
TOP.VexRiscv.decode_arbitration_removeIt
TOP.VexRiscv.execute_arbitration_removeIt
TOP.VexRiscv.memory_arbitration_removeIt
TOP.VexRiscv.writeBack_arbitration_removeIt
TOP.VexRiscv.execute_arbitration_isValid
[pattern_trace] 1
[pattern_trace] 0