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FPU now implement a less pessismitic dirty logic

This commit is contained in:
Dolu1990 2023-02-08 15:16:53 +01:00
parent 3ae51cdeb8
commit 33e820bdf9
2 changed files with 6 additions and 2 deletions
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1
src/main/scala/vexriscv/ip/fpu/Interface.scala
View File

@ -144,6 +144,7 @@ case class FpuParameter( withDouble : Boolean,
case class FpuFlags() extends Bundle{
val NX, UF, OF, DZ, NV = Bool()
def any = List(NX, UF, OF, DZ, NV).orR
}
case class FpuCompletion() extends Bundle{

7
src/main/scala/vexriscv/plugin/FpuPlugin.scala
View File

@ -216,8 +216,8 @@ class FpuPlugin(externalFpu : Boolean = false,
val fs = Reg(Bits(2 bits)) init(1)
val sd = fs === 3
when(stages.last.arbitration.isFiring && stages.last.input(FPU_ENABLE) && stages.last.input(FPU_OPCODE) =/= FpuOpcode.STORE){
fs := 3 //DIRTY
when(port.completion.fire && (port.completion.written || port.completion.flags.any)){
fs := 3
}
when(List(CSR.FRM, CSR.FCSR, CSR.FFLAGS).map(id => service.isWriting(id)).orR){
fs := 3
@ -298,6 +298,9 @@ class FpuPlugin(externalFpu : Boolean = false,
when(!arbitration.isStuck && !arbitration.isRemoved){
csr.flags.NV setWhen(port.rsp.NV)
csr.flags.NX setWhen(port.rsp.NX)
when(port.rsp.NV || port.rsp.NX){
csr.fs := 3
}
}
}
when(!port.rsp.valid){