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VexRiscv
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Enable scala 2.13 compatibility

This commit is contained in:
Dolu1990 2021-12-20 09:38:02 +01:00
parent a340798840
commit 34e5cafb75
4 changed files with 11 additions and 7 deletions
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2
src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala
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@ -13,6 +13,8 @@ import spinal.lib.eda.bench.Report
import scala.sys.process._
import scala.collection.Seq
object IcestormFlow {
def doCmd(cmd : Seq[String], path : String): String ={
println(cmd)

9
src/main/scala/vexriscv/VexRiscv.scala
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@ -4,6 +4,7 @@ import vexriscv.plugin._
import spinal.core._
import scala.collection.mutable.ArrayBuffer
import scala.collection.Seq
object VexRiscvConfig{
def apply(withMemoryStage : Boolean, withWriteBackStage : Boolean, plugins : Seq[Plugin[VexRiscv]]): VexRiscvConfig = {
@ -135,10 +136,10 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{
plugins ++= config.plugins
//regression usage
val lastStageInstruction = CombInit(stages.last.input(config.INSTRUCTION)) keep() addAttribute (Verilator.public)
val lastStagePc = CombInit(stages.last.input(config.PC)) keep() addAttribute (Verilator.public)
val lastStageIsValid = CombInit(stages.last.arbitration.isValid) keep() addAttribute (Verilator.public)
val lastStageIsFiring = CombInit(stages.last.arbitration.isFiring) keep() addAttribute (Verilator.public)
val lastStageInstruction = CombInit(stages.last.input(config.INSTRUCTION)).keep().addAttribute (Verilator.public)
val lastStagePc = CombInit(stages.last.input(config.PC)).keep().addAttribute(Verilator.public)
val lastStageIsValid = CombInit(stages.last.arbitration.isValid).keep().addAttribute(Verilator.public)
val lastStageIsFiring = CombInit(stages.last.arbitration.isFiring).keep().addAttribute(Verilator.public)
//Verilator perf
decode.arbitration.removeIt.noBackendCombMerge

2
src/main/scala/vexriscv/demo/Briey.scala
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@ -24,7 +24,7 @@ import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal}
import spinal.lib.system.debugger.{JtagAxi4SharedDebugger, JtagBridge, SystemDebugger, SystemDebuggerConfig}
import scala.collection.mutable.ArrayBuffer
import scala.collection.Seq
case class BrieyConfig(axiFrequency : HertzNumber,
onChipRamSize : BigInt,

5
src/main/scala/vexriscv/demo/Murax.scala
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@ -16,6 +16,7 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
import spinal.lib.com.spi.ddr._
import spinal.lib.bus.simple._
import scala.collection.mutable.ArrayBuffer
import scala.collection.Seq
/**
* Created by PIC32F_USER on 28/07/2017.
@ -313,13 +314,13 @@ case class Murax(config : MuraxConfig) extends Component{
//******** Memory mappings *********
val apbDecoder = Apb3Decoder(
master = apbBridge.io.apb,
slaves = apbMapping
slaves = apbMapping.toSeq
)
val mainBusDecoder = new Area {
val logic = new MuraxPipelinedMemoryBusDecoder(
master = mainBusArbiter.io.masterBus,
specification = mainBusMapping,
specification = mainBusMapping.toSeq,
pipelineMaster = pipelineMainBus
)
}