Spinal 1.0.2 sim update

build.sbt

@@ -9,8 +9,8 @@ scalaVersion := "2.11.6"
 EclipseKeys.withSource := true
 
 libraryDependencies ++= Seq(
-  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.1",
-  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.1",
+  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.2",
+  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.2",
   "org.yaml" % "snakeyaml" % "1.8"
 )
 

src/test/scala/vexriscv/MuraxSim.scala

@@ -2,7 +2,7 @@ package vexriscv
 
 import spinal.sim._
 import spinal.core._
-import spinal.core.SimManagedApi._
+import spinal.core.sim._
 import vexriscv.demo.{Murax, MuraxConfig}
 
 import java.awt.Graphics

src/test/scala/vexriscv/TcpJtag.scala

@@ -3,7 +3,7 @@ package vexriscv
 import java.io.{InputStream, OutputStream}
 import java.net.ServerSocket
 
-import spinal.core.SimManagedApi._
+import spinal.core.sim._
 import spinal.lib.com.jtag.Jtag
 
 import scala.concurrent.Future

src/test/scala/vexriscv/UartDecoder.scala

@@ -1,7 +1,7 @@
 package vexriscv
 
 import spinal.sim._
-import spinal.core.SimManagedApi._
+import spinal.core.sim._
 import spinal.core.{Bool, assert}
 
 object UartDecoder {

src/test/scala/vexriscv/UartEncoder.scala

@@ -1,8 +1,8 @@
 package vexriscv
 
 import spinal.sim._
+import spinal.core.sim._
 import spinal.core.Bool
-import spinal.core.SimManagedApi._
 
 object UartEncoder {
   def apply(uartPin : Bool, baudPeriod : Long) = fork{