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Avalon add read response support. 

Fix debug instruction injection and IBusSimplePlugin interraction
This commit is contained in:
Charles Papon 2017-07-21 20:39:54 +02:00
parent 54f785b1a3
commit 37c338ec98
5 changed files with 18 additions and 7 deletions
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3
src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala
View File

@ -42,6 +42,7 @@ object DBusSimpleBus{
addressWidth = 32,
dataWidth = 32).copy(
useByteEnable = true,
useResponse = true,
maximumPendingReadTransactions = 1
)
}
@ -124,7 +125,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
cmdStage.ready := mm.waitRequestn
rsp.ready :=mm.readDataValid
rsp.error := False //TODO
rsp.error := mm.response =/= AvalonMM.Response.OKAY
rsp.data := mm.readData
mm

5
src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala
View File

@ -39,6 +39,7 @@ object IBusSimpleBus{
addressWidth = 32,
dataWidth = 32
).getReadOnlyConfig.copy(
useResponse = true,
maximumPendingReadTransactions = 1
)
}
@ -88,7 +89,7 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste
rsp.ready := mm.readDataValid
rsp.inst := mm.readData
rsp.error := False //TODO
rsp.error := mm.response =/= AvalonMM.Response.OKAY
mm
}
@ -140,6 +141,8 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean)
}
}
fetch.insert(IBUS_ACCESS_ERROR) clearWhen(!fetch.arbitration.isValid) //Avoid interference with instruction injection from the debug plugin
if(interfaceKeepData)
fetch.arbitration.haltIt setWhen(fetch.arbitration.isValid && !iBus.rsp.ready)
else

3
src/main/scala/VexRiscv/ip/DataCache.scala
View File

@ -41,6 +41,7 @@ case class DataCacheConfig( cacheSize : Int,
useByteEnable = true,
constantBurstBehavior = true,
burstOnBurstBoundariesOnly = true,
useResponse = true,
maximumPendingReadTransactions = 2
)
}
@ -275,7 +276,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
cmd.ready := mm.waitRequestn
rsp.valid := mm.readDataValid
rsp.data := mm.readData
rsp.error := False
rsp.error := mm.response =/= AvalonMM.Response.OKAY
mm
}

3
src/main/scala/VexRiscv/ip/InstructionCache.scala
View File

@ -37,6 +37,7 @@ case class InstructionCacheConfig( cacheSize : Int,
dataWidth = memDataWidth,
burstCountWidth = log2Up(burstSize + 1)).getReadOnlyConfig.copy(
linewrapBursts = wrappedMemAccess,
useResponse = true,
constantBurstBehavior = true
)
@ -154,7 +155,7 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
cmd.ready := mm.waitRequestn
rsp.valid := mm.readDataValid
rsp.data := mm.readData
rsp.error := False
rsp.error := mm.response =/= AvalonMM.Response.OKAY
mm
}
}

11
src/test/cpp/regression/main.cpp
View File

@ -528,9 +528,11 @@ public:
IBusSimpleAvalonRsp rsp = rsps.front(); rsps.pop();
top->iBusAvalon_readDataValid = 1;
top->iBusAvalon_readData = rsp.data;
top->iBusAvalon_response = rsp.error ? 3 : 0;
} else {
top->iBusAvalon_readDataValid = 0;
top->iBusAvalon_readData = VL_RANDOM_I(32);
top->iBusAvalon_response = VL_RANDOM_I(2);
}
if(ws->iStall)
top->iBusAvalon_waitRequestn = VL_RANDOM_I(7) < 100;
@ -625,8 +627,9 @@ public:
if(!tasks.empty() && (!ws->iStall || VL_RANDOM_I(7) < 100)){
uint32_t &address = tasks.front().address;
uint32_t &pendingCount = tasks.front().pendingCount;
bool error;
ws->iBusAccess(address,&top->iBusAvalon_readData,&error);
//top->iBus_rsp_payload_error = error; //TODO
top->iBusAvalon_response = error ? 3 : 0;
pendingCount--;
address = (address & ~0x1F) + ((address + 4) & 0x1F);
top->iBusAvalon_readDataValid = 1;
@ -723,9 +726,11 @@ public:
DBusSimpleAvalonRsp rsp = rsps.front(); rsps.pop();
top->dBusAvalon_readDataValid = 1;
top->dBusAvalon_readData = rsp.data;
top->dBusAvalon_response = rsp.error ? 3 : 0;
} else {
top->dBusAvalon_readDataValid = 0;
top->dBusAvalon_readData = VL_RANDOM_I(32);
top->dBusAvalon_response = VL_RANDOM_I(2);
}
if(ws->iStall)
top->dBusAvalon_waitRequestn = VL_RANDOM_I(7) < 100;
@ -837,13 +842,13 @@ public:
if(!rsps.empty() && (!ws->dStall || VL_RANDOM_I(7) < 100)){
DBusCachedAvalonTask rsp = rsps.front();
rsps.pop();
//top->dBus_rsp_payload_error = rsp.error; //TODO
top->dBusAvalon_response = rsp.error ? 3 : 0;
top->dBusAvalon_readData = rsp.data;
top->dBusAvalon_readDataValid = 1;
} else{
top->dBusAvalon_readDataValid = 0;
top->dBusAvalon_readData = VL_RANDOM_I(32);
//top->dBus_rsp_payload_error = VL_RANDOM_I(1); //TODO
top->dBusAvalon_response = VL_RANDOM_I(2); //TODO
}
top->dBusAvalon_waitRequestn = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1);