Add Synthesis bench
This commit is contained in:
Dolu1990
parent
6930e76042
commit
37ea699c55
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@ -9,87 +9,87 @@ import spinal.core._
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* Created by spinalvm on 15.06.17.
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*/
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object GenFull extends App{
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SpinalVerilog(
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gen = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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catchMemoryTranslationMiss = true,
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asyncTagMemory = false,
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twoStageLogic = true
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),
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askMemoryTranslation = true,
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 4
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)
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def cpu() = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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catchMemoryTranslationMiss = true,
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asyncTagMemory = false,
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twoStageLogic = true
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),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true,
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catchMemoryTranslationMiss = true
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),
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 6
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)
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askMemoryTranslation = true,
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 4
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)
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),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true,
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catchMemoryTranslationMiss = true
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),
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new MemoryTranslatorPlugin(
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tlbSize = 32,
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virtualRange = _(31 downto 28) === 0xC,
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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new FullBarrielShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new MulPlugin,
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new DivPlugin,
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new CsrPlugin(CsrPluginConfig.all),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true,
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prediction = DYNAMIC
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),
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new YamlPlugin("cpu0.yaml")
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)
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 6
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)
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),
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new MemoryTranslatorPlugin(
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tlbSize = 32,
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virtualRange = _(31 downto 28) === 0xC,
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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new FullBarrielShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new MulPlugin,
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new DivPlugin,
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new CsrPlugin(CsrPluginConfig.all),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true,
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prediction = DYNAMIC
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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)
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SpinalVerilog(cpu())
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}
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@ -0,0 +1,86 @@
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package VexRiscv.demo
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import VexRiscv.Plugin._
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import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig}
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import spinal.core._
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/**
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* Created by spinalvm on 15.06.17.
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*/
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object GenFullNoMmu extends App{
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def cpu() = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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catchMemoryTranslationMiss = true,
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asyncTagMemory = false,
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twoStageLogic = true
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)
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),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true,
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catchMemoryTranslationMiss = true
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)
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),
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new StaticMemoryTranslatorPlugin(
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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new FullBarrielShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new MulPlugin,
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new DivPlugin,
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new CsrPlugin(CsrPluginConfig.all),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true,
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prediction = DYNAMIC
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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)
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SpinalVerilog(cpu())
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}
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@ -8,49 +8,49 @@ import spinal.core._
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* Created by spinalvm on 15.06.17.
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*/
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object GenSmallest extends App{
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SpinalVerilog(
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gen = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, true),
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new CsrPlugin(CsrPluginConfig.smallest),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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),
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new YamlPlugin("cpu0.yaml")
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)
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def cpu() = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, true),
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new CsrPlugin(CsrPluginConfig.smallest),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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)
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SpinalVerilog(cpu())
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}
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@ -0,0 +1,55 @@
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package VexRiscv.demo
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import VexRiscv.Plugin._
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import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig}
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import spinal.core._
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/**
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* Created by spinalvm on 15.06.17.
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*/
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object GenSmallestNoCsr extends App{
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def cpu() = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, true),
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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)
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SpinalVerilog(cpu())
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}
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@ -0,0 +1,45 @@
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package VexRiscv.demo
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import spinal.core.SpinalVerilog
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import spinal.lib.eda.bench.{Bench, AlteraStdTargets, Rtl}
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/**
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* Created by PIC32F_USER on 16/07/2017.
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*/
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object SynthesisBench {
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def main(args: Array[String]) {
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val smallestNoCsr = new Rtl {
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override def getName(): String = "VexRiscv smallest no CSR"
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override def getRtlPath(): String = "VexRiscvSmallestNoCsr.v"
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SpinalVerilog(GenSmallestNoCsr.cpu().setDefinitionName(getRtlPath().split("\\.").head))
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}
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val smallest = new Rtl {
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override def getName(): String = "VexRiscv smallest"
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override def getRtlPath(): String = "VexRiscvSmallest.v"
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SpinalVerilog(GenSmallest.cpu().setDefinitionName(getRtlPath().split("\\.").head))
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}
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val fullNoMmu = new Rtl {
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override def getName(): String = "VexRiscv full no MMU"
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override def getRtlPath(): String = "VexRiscvFullNoMmu.v"
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SpinalVerilog(GenFullNoMmu.cpu().setDefinitionName(getRtlPath().split("\\.").head))
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}
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val full = new Rtl {
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override def getName(): String = "VexRiscv full"
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override def getRtlPath(): String = "VexRiscvFull.v"
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SpinalVerilog(GenFull.cpu().setDefinitionName(getRtlPath().split("\\.").head))
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}
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val rtls = List(smallestNoCsr, smallest, fullNoMmu, full)
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val targets = AlteraStdTargets(
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quartusCycloneIIPath = "D:/altera/13.0sp1/quartus/bin64",
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quartusCycloneIVPath = "D:/altera_lite/15.1/quartus/bin64",
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quartusCycloneVPath = "D:/altera_lite/15.1/quartus/bin64"
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)
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Bench(rtls, targets, "E:/tmp/")
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}
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}
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