few more var parameters
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a755d839b3
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@ -46,7 +46,7 @@ case class CsrPluginConfig(
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misaExtensionsInit : Int,
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misaAccess : CsrAccess,
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mtvecAccess : CsrAccess,
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mtvecInit : BigInt,
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var mtvecInit : BigInt,
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mepcAccess : CsrAccess,
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mscratchGen : Boolean,
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mcauseAccess : CsrAccess,
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@ -458,7 +458,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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}
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override def getVexRiscvRegressionArgs() = List(s"SUPERVISOR=${if(config.supervisorGen) "yes" else "no"}, CSR=yes")
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override def getVexRiscvRegressionArgs() = List(s"SUPERVISOR=${if(config.supervisorGen) "yes" else "no"} CSR=yes")
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var exceptionPendings : Vec[Bool] = null
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override def isExceptionPending(stage : Stage): Bool = exceptionPendings(pipeline.stages.indexOf(stage))
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@ -38,7 +38,7 @@ case class MmuPort(bus : MemoryTranslatorBus, priority : Int, args : MmuPortConf
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case class MmuPortConfig(portTlbSize : Int, latency : Int = 0, earlyRequireMmuLockup : Boolean = false, earlyCacheHits : Boolean = false)
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class MmuPlugin(ioRange : UInt => Bool,
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class MmuPlugin(var ioRange : UInt => Bool,
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virtualRange : UInt => Bool = address => True,
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// allowUserIo : Boolean = false,
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enableMmuInMachineMode : Boolean = false) extends Plugin[VexRiscv] with MemoryTranslator {
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