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Fix fpu csr access on fs===0 now also trap

This commit is contained in:
Dolu1990 2023-02-08 14:44:04 +01:00
parent cbc89093b3
commit 3ae51cdeb8
1 changed files with 7 additions and 5 deletions
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8
src/main/scala/vexriscv/plugin/FpuPlugin.scala
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@ -229,14 +229,16 @@ class FpuPlugin(externalFpu : Boolean = false,
service.r(CSR.SSTATUS, 31, sd) service.r(CSR.SSTATUS, 31, sd)
service.r(CSR.MSTATUS, 31, sd) service.r(CSR.MSTATUS, 31, sd)
when(fs === 0) { val accessFpuCsr = False
for (csr <- List(CSR.FRM, CSR.FCSR, CSR.FFLAGS)) { for (csr <- List(CSR.FRM, CSR.FCSR, CSR.FFLAGS)) {
service.during(csr) { service.during(csr) {
accessFpuCsr := True
}
}
when(accessFpuCsr && fs === 0) {
service.forceFailCsr() service.forceFailCsr()
} }
} }
}
}
decode plug new Area{ decode plug new Area{
import decode._ import decode._