better travis timings
travis job naming reduce verilator cache size Fix dcache test timeout travis cleaning travis wip verilator wip fix java 10 compilation Travis wip travis rework
This commit is contained in:
Charles Papon
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06e63252e4
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103
.travis.yml
103
.travis.yml
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@ -1,67 +1,84 @@
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language: scala
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dist: xenial
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notifications:
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email:
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on_success: never
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# See 'project/Version.scala'
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scala:
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- 2.11.6
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- 2.11.12
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sbt_args: -no-colors -J-Xss2m
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script:
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- export VEXRISCV_REGRESSION_FREERTOS_COUNT=no
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- export VEXRISCV_REGRESSION_THREAD_COUNT=1
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- sbt -jvm-opts travis/jvmopts.compile compile
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- sbt -jvm-opts travis/jvmopts.test test
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addons:
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apt:
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sources:
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- ubuntu-toolchain-r-test
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packages:
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- git
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- make
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- autoconf
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- g++
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- flex
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- bison
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jdk:
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- oraclejdk8
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# - oraclejdk7
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# - openjdk7
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- openjdk10
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env:
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- VEXRISCV_REGRESSION_CONFIG_COUNT=0
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- VEXRISCV_REGRESSION_CONFIG_COUNT=5
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- VEXRISCV_REGRESSION_CONFIG_COUNT=5
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- VEXRISCV_REGRESSION_CONFIG_COUNT=5
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- VEXRISCV_REGRESSION_CONFIG_COUNT=5
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jobs:
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include:
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- stage: prepare cache-verilator
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script:
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- cp scripts/regression/verilator.mk $HOME/makefile
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- cd $HOME
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- make verilator_binary
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- &test
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stage: Test
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name: TEST_DHRYSTONE
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script:
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- make regression_dhrystone -C scripts/regression
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- <<: *test
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stage: Test
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name: TEST_BAREMETAL
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script:
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- make regression_random_baremetal -C scripts/regression
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- <<: *test
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stage: Test
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name: TEST_BAREMETAL
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script:
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- make regression_random_baremetal -C scripts/regression
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- <<: *test
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stage: Test
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name: TEST_MIXED
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script:
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- make regression_random -C scripts/regression
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- <<: *test
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stage: Test
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name: TEST_LINUX
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script:
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- make regression_random_linux -C scripts/regression
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- <<: *test
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stage: Test
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name: TEST_LINUX
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script:
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- make regression_random_linux -C scripts/regression
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before_install:
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# JDK fix
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- cat /etc/hosts # optionally check the content *before*
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- sudo hostname "$(hostname | cut -c1-63)"
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- sed -e "s/^\\(127\\.0\\.0\\.1.*\\)/\\1 $(hostname | cut -c1-63)/" /etc/hosts | sudo tee /etc/hosts
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- cat /etc/hosts # optionally check the content *after*
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- cd ..
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# Verilator
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- sudo apt-get install git make autoconf g++ flex bison -y # First time prerequisites
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- wget https://www.veripool.org/ftp/verilator-4.012.tgz
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- tar xvzf verilator*.t*gz
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- cd verilator*
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- ./configure
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- make -j$(nproc)
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- sudo make install
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- cd ..
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- git clone https://github.com/SpinalHDL/SpinalHDL.git -b dev
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- cd VexRiscv
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- git submodule update --init --recursive
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#- curl -T README.md -udolu1990:$BINTRAY_KEY https://api.bintray.com/content/spinalhdl/VexRiscv/test/0.0.4/README.md
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#- curl -X POST -udolu1990:$BINTRAY_KEY https://api.bintray.com/content/spinalhdl/VexRiscv/test/0.0.4/publish
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#- sbt compile
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- export VERILATOR_ROOT=$HOME/verilator
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- export PATH=$VERILATOR_ROOT/bin:$PATH
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before_cache:
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# Tricks to avoid unnecessary cache updates
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- find $HOME/.ivy2 -name "ivydata-*.properties" -delete
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- find $HOME/.sbt -name "*.lock" -delete
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- rm -fv $HOME/.ivy2/.sbt.ivy.lock
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- find $HOME/.ivy2/cache -name "ivydata-*.properties" -print -delete
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- find $HOME/.sbt -name "*.lock" -print -delete
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cache:
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directories:
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- $HOME/.ivy2/cache
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- $HOME/.sbt/boot/
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- verilator-4.012
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- $HOME/.sbt
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- $HOME/verilator
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@ -0,0 +1,2 @@
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verilator*
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!verilator.mk
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@ -0,0 +1,7 @@
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.ONESHELL:
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include verilator.mk
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include regression.mk
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@ -0,0 +1,32 @@
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.ONESHELL:
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regression_random:
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cd ../..
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export VEXRISCV_REGRESSION_CONFIG_COUNT=4
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export VEXRISCV_REGRESSION_FREERTOS_COUNT=no
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export VEXRISCV_REGRESSION_THREAD_COUNT=1
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sbt "testOnly vexriscv.TestIndividualFeatures"
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regression_random_linux:
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cd ../..
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export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=1.0
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export VEXRISCV_REGRESSION_CONFIG_COUNT=3
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export VEXRISCV_REGRESSION_FREERTOS_COUNT=no
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export VEXRISCV_REGRESSION_THREAD_COUNT=1
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sbt "testOnly vexriscv.TestIndividualFeatures"
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regression_random_baremetal:
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cd ../..
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export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=0.0
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export VEXRISCV_REGRESSION_CONFIG_COUNT=50
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export VEXRISCV_REGRESSION_FREERTOS_COUNT=no
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export VEXRISCV_REGRESSION_THREAD_COUNT=1
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sbt "testOnly vexriscv.TestIndividualFeatures"
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regression_dhrystone:
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cd ../..
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sbt "testOnly vexriscv.DhrystoneBench"
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@ -0,0 +1,20 @@
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.ONESHELL:
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verilator/configure:
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rm -rf verilator*
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wget https://www.veripool.org/ftp/verilator-4.012.tgz
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tar xvzf verilator*.t*gz
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mv verilator-4.012 verilator
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verilator/Makefile: verilator/configure
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cd verilator
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./configure
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verilator/bin/verilator_bin: verilator/Makefile
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cd verilator
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make -j$(shell nproc)
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rm -rf src/obj_dbg
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rm -rf src/obj_opt
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verilator_binary: verilator/bin/verilator_bin
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@ -3680,7 +3680,7 @@ int main(int argc, char **argv, char **env) {
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redo(REDO,WorkspaceRegression("icache").withRiscvRef()->loadHex("../raw/icache/build/icache.hex")->bootAt(0x80000000u)->run(50e3););
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#endif
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#ifdef DBUS_CACHED
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redo(REDO,WorkspaceRegression("dcache").loadHex("../raw/dcache/build/dcache.hex")->bootAt(0x80000000u)->run(500e3););
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redo(REDO,WorkspaceRegression("dcache").loadHex("../raw/dcache/build/dcache.hex")->bootAt(0x80000000u)->run(2500e3););
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#endif
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#ifdef MMU
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@ -75,7 +75,7 @@ object MuraxSim {
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})
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setAlignmentX(awt.Component.CENTER_ALIGNMENT)
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})
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setDefaultCloseOperation(JFrame.EXIT_ON_CLOSE)
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setDefaultCloseOperation(WindowConstants.EXIT_ON_CLOSE)
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pack()
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setVisible(true)
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println(s"Seed=$seed")
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for(i <- 0 until sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_COUNT", "100").toInt){
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var positions : List[VexRiscvPosition] = null
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val universe = VexRiscvUniverse.universes.filter(e => rand.nextBoolean())
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var universe = mutable.HashSet[VexRiscvUniverse]()
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if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_LINUX_RATE", "0.5").toDouble > Math.random()) universe += VexRiscvUniverse.CATCH_ALL
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do{
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positions = dimensions.map(d => d.randomPosition(universe, rand))
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positions = dimensions.map(d => d.randomPosition(universe.toList, rand))
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}while(!positions.forall(_.isCompatibleWith(positions)))
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val testSeed = rand.nextInt()
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