mirror of
https://github.com/SpinalHDL/VexRiscv.git
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3b0f2e9551
travis job naming reduce verilator cache size Fix dcache test timeout travis cleaning travis wip verilator wip fix java 10 compilation Travis wip travis rework
20 lines
405 B
Makefile
20 lines
405 B
Makefile
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.ONESHELL:
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verilator/configure:
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rm -rf verilator*
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wget https://www.veripool.org/ftp/verilator-4.012.tgz
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tar xvzf verilator*.t*gz
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mv verilator-4.012 verilator
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verilator/Makefile: verilator/configure
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cd verilator
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./configure
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verilator/bin/verilator_bin: verilator/Makefile
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cd verilator
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make -j$(shell nproc)
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rm -rf src/obj_dbg
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rm -rf src/obj_opt
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verilator_binary: verilator/bin/verilator_bin
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