Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files

This commit is contained in:
Dolu1990 2018-01-20 18:29:33 +01:00
parent f5d5b91f7a
commit 3b3bbd48b9
17 changed files with 37 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitignore vendored
View File

@ -41,7 +41,7 @@ obj_dir
*.regTrace
*.tcl
*.o
*.bin
simWorkspace/
tmp/

4
build.sbt
View File

@ -9,8 +9,8 @@ scalaVersion := "2.11.6"
EclipseKeys.withSource := true
libraryDependencies ++= Seq(
"com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.2",
"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.2",
"com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.3",
"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.3",
"org.yaml" % "snakeyaml" % "1.8"
)

7
scripts/Murax/iCE40-hx8k_breakout_board/makefile
View File

@ -8,8 +8,10 @@ generate :
../../../Murax.v :
(cd ../../..; sbt "run-main vexriscv.demo.Murax")
bin/toplevel.blif : ${VERILOG}
bin/toplevel.blif : ${VERILOG} ../../../Murax.v*.bin
mkdir -p bin
rm -f Murax.v*.bin
cp ../../../Murax.v*.bin . | true
yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG}
bin/toplevel.asc : toplevel.pcf bin/toplevel.blif
@ -27,4 +29,5 @@ prog : bin/toplevel.bin
sudo iceprog -S bin/toplevel.bin
clean :
rm -rf bin
rm -rf bin
rm -f Murax.v*.bin

3
scripts/Murax/iCE40HX8K-EVB/makefile
View File

@ -10,6 +10,8 @@ generate :
bin/toplevel.blif : ${VERILOG}
mkdir -p bin
rm -f Murax.v*.bin
cp ../../../Murax.v*.bin . | true
yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG}
bin/toplevel.asc : toplevel.pcf bin/toplevel.blif
@ -31,3 +33,4 @@ sudo-prog : bin/toplevel.bin
clean :
rm -rf bin
rm -f Murax.v*.bin

4
src/main/scala/vexriscv/TestsWorkspace.scala
View File

@ -96,7 +96,7 @@ object TestsWorkspace {
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = true
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(
@ -197,7 +197,7 @@ object TestsWorkspace {
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = true
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(

2
src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala
View File

@ -29,7 +29,7 @@ object GenCustomSimdAdd extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = true
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(

2
src/main/scala/vexriscv/demo/GenFull.scala
View File

@ -63,7 +63,7 @@ object GenFull extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = true
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(

2
src/main/scala/vexriscv/demo/GenFullNoMmu.scala
View File

@ -54,7 +54,7 @@ object GenFullNoMmu extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = true
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(

2
src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala
View File

@ -29,7 +29,7 @@ object GenFullNoMmuNoCache extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = true
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(

2
src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala
View File

@ -29,7 +29,7 @@ object GenSmallAndProductive extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = true
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(

2
src/main/scala/vexriscv/demo/GenSmallest.scala
View File

@ -29,7 +29,7 @@ object GenSmallest extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = true
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(

2
src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala
View File

@ -28,7 +28,7 @@ object GenSmallestNoCsr extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = true
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(

4
src/main/scala/vexriscv/demo/Murax.scala
View File

@ -71,7 +71,7 @@ object MuraxConfig{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = true
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(
@ -325,4 +325,4 @@ object MuraxWithRamInit{
def main(args: Array[String]) {
SpinalVerilog(Murax(MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")))
}
}
}

5
src/test/cpp/briey/makefile
View File

@ -45,12 +45,15 @@ all: clean compile
run: compile
./obj_dir/VBriey
verilate:
verilate: ../../../../Briey.v
rm -f Briey.v*.bin
cp ../../../../Briey.v*.bin . | true
verilator -cc ../../../../Briey.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp
compile: verilate
make -j -C obj_dir/ -f VBriey.mk VBriey
clean:
rm -f Briey.v*.bin
rm -rf obj_dir

7
src/test/cpp/murax/makefile
View File

@ -28,12 +28,15 @@ all: clean compile
run: compile
./obj_dir/VMurax
verilate:
verilator -cc ../../../../Murax.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp
verilate: ../../../../Murax.v
rm -f Murax.v*.bin
cp ../../../../Murax.v*.bin . | true
verilator -I../../../.. -cc ../../../../Murax.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp
compile: verilate
make -j -C obj_dir/ -f VMurax.mk VMurax
clean:
rm -rf obj_dir
rm -f Murax.v*.bin

5
src/test/cpp/regression/makefile
View File

@ -99,7 +99,9 @@ all: clean run
run: compile
./obj_dir/VVexRiscv
verilate:
verilate: ../../../../VexRiscv.v
rm -f VexRiscv.v*.bin
cp ../../../../VexRiscv.v*.bin . | true
verilator -cc ../../../../VexRiscv.v -O3 -CFLAGS -std=c++11 -LDFLAGS -pthread ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-UNOPTFLAT -Wno-WIDTH --x-assign unique --exe main.cpp
compile: verilate
@ -107,4 +109,5 @@ compile: verilate
clean:
rm -rf obj_dir
rm -f VexRiscv.v*.bin

4
src/test/scala/vexriscv/MuraxSim.scala
View File

@ -20,8 +20,8 @@ import scala.collection.mutable
object MuraxSim {
def main(args: Array[String]): Unit = {
def config = MuraxConfig.default.copy(onChipRamSize = 256 kB)
// def config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")
// def config = MuraxConfig.default.copy(onChipRamSize = 256 kB)
def config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")
SimConfig.allOptimisation.compile(new Murax(config)).doSimUntilVoid{dut =>
val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong