Fix cpu sending instruction memory request while being halted by the DebugPlugin

This commit is contained in:
Charles Papon 2017-07-29 18:20:22 +02:00
parent 43253f61c1
commit 3b66d986a8
4 changed files with 7 additions and 8 deletions

View file

@ -187,7 +187,7 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] {
}
when(haltIt) {
prefetch.arbitration.haltIt := True
prefetch.arbitration.haltItByOther := True
}
when(stepIt && prefetch.arbitration.isFiring) {

View file

@ -6,9 +6,8 @@ import spinal.lib._
import scala.collection.mutable.ArrayBuffer
class PcManagerSimplePlugin(resetVector : BigInt, fastPcCalculation : Boolean = false) extends Plugin[VexRiscv] with JumpService{
class PcManagerSimplePlugin(resetVector : BigInt,
fastPcCalculation : Boolean = false) extends Plugin[VexRiscv] with JumpService{
//FetchService interface
case class JumpInfo(interface : Flow[UInt], stage: Stage)
val jumpInfos = ArrayBuffer[JumpInfo]()

View file

@ -10,6 +10,6 @@ class SingleInstructionLimiterPlugin() extends Plugin[VexRiscv] {
import pipeline._
import pipeline.config._
prefetch.arbitration.haltIt.setWhen(List(fetch,decode,execute,memory,writeBack).map(_.arbitration.isValid).orR)
prefetch.arbitration.haltItByOther.setWhen(List(fetch,decode,execute,memory,writeBack).map(_.arbitration.isValid).orR)
}
}

View file

@ -1,10 +1,10 @@
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Sat Jul 29 00:24:49 2017
[*] Sat Jul 29 10:39:29 2017
[*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/murax/Murax.vcd"
[dumpfile_mtime] "Sat Jul 29 00:24:44 2017"
[dumpfile_size] 177335125
[dumpfile_mtime] "Sat Jul 29 10:39:12 2017"
[dumpfile_size] 230220943
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/murax/murax.gtkw"
[timestart] 56764536000
[size] 1776 953