Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv
This commit is contained in:
commit
3d5e941aef
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@ -1,6 +1,7 @@
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*.class
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*.log
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*.bak
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.*.swp
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# sbt specific
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.cache/
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@ -46,4 +47,4 @@ obj_dir
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simWorkspace/
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tmp/
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/archive.tar.gz
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*.out32
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*.out32
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@ -63,6 +63,12 @@ object DBusSimpleBus{
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useBTE = true,
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useCTI = true
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)
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def getPipelinedMemoryBusConfig() = PipelinedMemoryBusConfig(
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addressWidth = 32,
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dataWidth = 32
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)
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}
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case class DBusSimpleBus() extends Bundle with IMasterSlave{
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@ -178,7 +184,8 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
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}
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def toPipelinedMemoryBus() : PipelinedMemoryBus = {
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val bus = PipelinedMemoryBus(32,32)
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val pipelinedMemoryBusConfig = DBusSimpleBus.getPipelinedMemoryBusConfig()
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val bus = PipelinedMemoryBus(pipelinedMemoryBusConfig)
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bus.cmd.valid := cmd.valid
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bus.cmd.write := cmd.wr
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bus.cmd.address := cmd.address.resized
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@ -59,6 +59,11 @@ object IBusSimpleBus{
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useBTE = true,
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useCTI = true
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)
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def getPipelinedMemoryBusConfig() = PipelinedMemoryBusConfig(
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addressWidth = 32,
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dataWidth = 32
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)
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}
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@ -136,7 +141,8 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit
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}
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def toPipelinedMemoryBus(): PipelinedMemoryBus = {
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val bus = PipelinedMemoryBus(32,32)
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val pipelinedMemoryBusConfig = IBusSimpleBus.getPipelinedMemoryBusConfig()
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val bus = PipelinedMemoryBus(pipelinedMemoryBusConfig)
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bus.cmd.arbitrationFrom(cmd)
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bus.cmd.address := cmd.pc.resized
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bus.cmd.write := False
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@ -281,4 +287,4 @@ class IBusSimplePlugin(resetVector : BigInt,
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}
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}
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}
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}
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}
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